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公开(公告)号：US20120284548A1
公开(公告)日：2012-11-08
申请号：US13552327
申请日：2012-07-18
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/3287 , G06F9/3001 , G06F9/30105 , G06F9/30192 , Y02D10/171
摘要： A method and system for reducing power consumption when processing mathematical operations. Power may be reduced in processor hardware devices that receive one or more operands from an execution unit that executes instructions. A circuit detects when at least one operand of multiple operands is a zero operand, prior to the operand being forwarded to an execution component for completing a mathematical operation. When at least one operand is a zero operand or at least one operand is “unordered”, a flag is set that triggers a gating of a clock signal. The gating of the clock signal disables one or more processing stages and/or devices, which perform the mathematical operation. Disabling the stages and/or devices enables computing the correct result of the mathematical operation on a reduced data path. When a device(s) is disabled, the device may be powered off until the device is again required by subsequent operations.
摘要翻译： 一种在处理数学运算时降低功耗的方法和系统。 在从执行指令的执行单元接收一个或多个操作数的处理器硬件设备中，功率可能会降低。 在将操作数转发到执行组件以完成数学运算之前，电路检测多个操作数的至少一个操作数是否为零操作数。 当至少一个操作数为零操作数或至少一个操作数无序时，会设置一个触发门控时钟信号的标志。 时钟信号的门控禁用执行数学运算的一个或多个处理级和/或器件。 禁用级和/或设备可以在减少的数据路径上计算数学运算的正确结果。 当设备被禁用时，可能会关闭设备电源，直到后续操作再次要求设备。
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公开(公告)号：US20100146023A1
公开(公告)日：2010-06-10
申请号：US12331702
申请日：2008-12-10
IPC分类号： G06F7/00
摘要： A shifter that includes a plurality of shift stages positioned within the shifter, and receiving and shifting input data to generate a shifted result, and a detection circuit coupled at an input of a final shift stage of the plurality of shifters, in a final stage within the shifter. The detection circuit receives a partially shifted vector at the input of the final shift stage along with a predetermined shift amount, and performing an all-one or all-zero detection operation using a portion of the partially shifted vector and the predetermined shift amount, in parallel, to a shifting operation performed by the final shift stage to generate the shifted result.
摘要翻译： 一种移位器，其包括位于所述移位器内的多个移位级，并且接收和移位输入数据以产生移位结果;以及检测电路，其耦合在所述多个移位器的最终移位级的输入端， 移位器。 检测电路在最终变速级的输入端接收预定的移位量的部分偏移矢量，并且使用部分偏移矢量的一部分和预定位移量进行全一或全零检测操作， 并行地移动到由最终变速级执行的换档操作以产生转换结果。
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公开(公告)号：US20100063987A1
公开(公告)日：2010-03-11
申请号：US12207067
申请日：2008-09-09
申请人： Maarten J. Boersma , K. Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
发明人： Maarten J. Boersma , K. Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
IPC分类号： G06F7/38
CPC分类号： G06F7/4991 , G06F7/483
摘要： In a binary floating point processor, the exponents of each of the various types of operands are recoded into an internal format, by biasing the exponents with the minimum exponent value of the result precision (“Emin”), i.e., the recoded value of the exponent is the represented value of the exponent minus Emin. Emin depends only on the result precision of the instruction that is currently being executed in the binary floating point processor. The exponent computations are then performed in this new format. The underflow check for all result precisions is a check against zero and overflow checks are performed against a positive number that depends on the result precision. The exponent values are in a 2's complement representation, so the underflow check simply becomes a check of the sign bit.
摘要翻译： 在二进制浮点处理器中，通过使用结果精度（“Emin”）的最小指数值偏移指数，即将重新编码的值转换为内部格式，将各种类型的操作数中的每一个的指数重新编码为内部格式 指数是指数减去Emin的表示值。 Emin仅取决于当前正在二进制浮点处理器中执行的指令的结果精度。 然后以这种新格式执行指数计算。 对所有结果精度的下溢检查是针对零的检查，并且针对取决于结果精度的正数执行溢出检查。 指数值为2的补码表示，因此下溢检查简单地成为对符号位的检查。
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14.发明授权Floating point unit with fused multiply add and method for calculating a result with a floating point unit 失效具有融合乘法的浮点单元和用浮点单元计算结果的方法公开(公告)号：US07461117B2
公开(公告)日：2008-12-02
申请号：US11055812
申请日：2005-02-11
申请人： Son Dao Trong , Juergen Haess , Christian Jacobi , Klaus Michael Kroener , Silvia Melitta Mueller , Jochen Preiss
发明人： Son Dao Trong , Juergen Haess , Christian Jacobi , Klaus Michael Kroener , Silvia Melitta Mueller , Jochen Preiss
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/5443
摘要： The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with an alignment logic (3) which uses the alignment shift amount to align the fraction (fb) of the addend operand, with a multiply logic (4) which multiplies the fractions of the multiplicand operands (fa, fc), with a adder logic (5) which adds the outputs of the alignment logic (3) and the multiply logic (4), with a normalization logic (6) which normalizes the output of the adder logic (5), which is characterized in that a leading zero logic (7) is provided which computes the number of leading zeros of the fraction of the addend operand (fb), and that a compare logic (8) is provided which based on the number of leading zeros and the alignment shift amount computes select signals that indicate whether the most significant bits of the alignment logic (3) output have all the same value in order to: a) control the carry logic of the adder logic (5) and/or b) control a stage of the normalization logic (6).
摘要翻译： 本发明提出了一种具有融合乘法运算的浮点单元（1），具有一个加数运算数（eb，fb）和两个被乘数运算符（ea，fa; ec，fc），其中移位量逻辑（2）基于 操作数（ea，eb和ec）的指数利用对准逻辑（3）计算对准偏移量，该对准逻辑（3）使用对准移位量来对齐加数操作数的分数（fb）与乘法逻辑（4） 将乘法器操作数（fa，fc）的分数与加法器逻辑（5）相乘，该逻辑（5）将对准逻辑（3）和乘法逻辑（4）的输出与归一化逻辑（6）进行归一化，归一化逻辑（6） 加法器逻辑（5）的特征在于提供一个前导零逻辑（7），其计算加法运算数（fb）的分数的前导零的数量，并且提供比较逻辑（8） 其基于前导零的数量和对准偏移量计算指示mo的选择信号 对准逻辑（3）输出的高有效位具有全部相同的值，以便：a）控制加法器逻辑（5）的进位逻辑和/或b）控制归一化逻辑（6）的阶段。
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公开(公告)号：US08626807B2
公开(公告)日：2014-01-07
申请号：US12350680
申请日：2009-01-08
IPC分类号： G06F7/00
CPC分类号： H03M7/24
摘要： A method for converting a signed fixed point number into a floating point number that includes reading an input number corresponding to a signed fixed point number to be converted, determining whether the input number is less than zero, setting a sign bit based upon whether the input number is less than zero or greater than or equal to zero, computing a first intermediate result by exclusive-ORing the input number with the sign bit, computing leading zeros of the first intermediate result, padding the first intermediate result based upon the sign bit, computing a second intermediate result by shifting the padded first intermediate result to the left by the leading zeros, computing an exponent portion and a fraction portion, conditionally incrementing the fraction portion based on the sign bit, correcting the exponent portion and the fraction portion if the incremented fraction portion overflows, and returning the floating point number.
摘要翻译： 一种用于将有符号固定点数转换为浮点数的方法，该浮点数包括读取与要转换的有符号固定点数相对应的输入数，确定输入数是否小于零，根据输入 数量小于零或大于或等于零，通过将输入数字与符号位进行异或运算来计算第一中间结果，计算第一中间结果的前导零，基于符号位填充第一中间结果， 通过将填充的第一中间结果向左移动前导零来计算第二中间结果，计算指数部分和分数部分，基于符号位有条件地增加分数部分，校正指数部分和分数部分，如果 递增分数部分溢出，返回浮点数。
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公开(公告)号：US08578196B2
公开(公告)日：2013-11-05
申请号：US13552327
申请日：2012-07-18
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/3287 , G06F9/3001 , G06F9/30105 , G06F9/30192 , Y02D10/171
摘要： A method and system for reducing power consumption when processing mathematical operations. Power may be reduced in processor hardware devices that receive one or more operands from an execution unit that executes instructions. A circuit detects when at least one operand of multiple operands is a zero operand, prior to the operand being forwarded to an execution component for completing a mathematical operation. When at least one operand is a zero operand or at least one operand is “unordered”, a flag is set that triggers a gating of a clock signal. The gating of the clock signal disables one or more processing stages and/or devices, which perform the mathematical operation. Disabling the stages and/or devices enables computing the correct result of the mathematical operation on a reduced data path. When a device(s) is disabled, the device may be powered off until the device is again required by subsequent operations.
摘要翻译： 一种在处理数学运算时降低功耗的方法和系统。 在从执行指令的执行单元接收一个或多个操作数的处理器硬件设备中，功率可能会降低。 在将操作数转发到执行组件以完成数学运算之前，电路检测多个操作数的至少一个操作数是否为零操作数。 当至少一个操作数为零操作数或至少一个操作数为“无序”时，设置触发时钟信号选通的标志。 时钟信号的门控禁用执行数学运算的一个或多个处理级和/或器件。 禁用级和/或设备可以在减少的数据路径上计算数学运算的正确结果。 当设备被禁用时，可能会关闭设备电源，直到后续操作再次要求设备。
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公开(公告)号：US08291003B2
公开(公告)日：2012-10-16
申请号：US12207067
申请日：2008-09-09
申请人： Maarten J. Boersma , K. Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
发明人： Maarten J. Boersma , K. Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
IPC分类号： G06F7/38
CPC分类号： G06F7/4991 , G06F7/483
摘要： In a binary floating point processor, the exponents of each of the various types of operands are recoded into an internal format, by biasing the exponents with the minimum exponent value of the result precision (“Emin”), i.e., the recoded value of the exponent is the represented value of the exponent minus Emin. Emin depends only on the result precision of the instruction that is currently being executed in the binary floating point processor. The exponent computations are then performed in this new format. The underflow check for all result precisions is a check against zero and overflow checks are performed against a positive number that depends on the result precision. The exponent values are in a 2's complement representation, so the underflow check simply becomes a check of the sign bit.
摘要翻译： 在二进制浮点处理器中，通过用结果精度（Emin）的最小指数值偏置指数，将各种类型的操作数中的每一个的指数重新编码为内部格式，即指数的重新编码值为 指数的代表值减去Emin。 Emin仅取决于当前正在二进制浮点处理器中执行的指令的结果精度。 然后以这种新格式执行指数计算。 对所有结果精度的下溢检查是针对零的检查，并且针对取决于结果精度的正数执行溢出检查。 指数值为2的补码表示，因此下溢检查简单地成为对符号位的检查。
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公开(公告)号：US08255726B2
公开(公告)日：2012-08-28
申请号：US12176191
申请日：2008-07-18
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/3287 , G06F9/3001 , G06F9/30105 , G06F9/30192 , Y02D10/171
摘要： A method, system and computer program product for reducing power consumption when processing mathematical operations. Power may be reduced in processor hardware devices that receive one or more operands from an execution unit that executes instructions. A circuit detects when at least one operand of multiple operands is a zero operand, prior to the operand being forwarded to an execution component for completing a mathematical operation. When at least one operand is a zero operand or at least one operand is “unordered”, a flag is set that triggers a gating of a clock signal. The gating of the clock signal disables one or more processing stages and/or devices, which perform the mathematical operation. Disabling the stages and/or devices enables computing the correct result of the mathematical operation on a reduced data path. When a device(s) is disabled, the device may be powered off until the device is again required by subsequent operations.
摘要翻译： 一种用于在处理数学运算时降低功耗的方法，系统和计算机程序产品。 在从执行指令的执行单元接收一个或多个操作数的处理器硬件设备中，功率可能会降低。 在将操作数转发到执行组件以完成数学运算之前，电路检测多个操作数的至少一个操作数是否为零操作数。 当至少一个操作数为零操作数或至少一个操作数为“无序”时，设置触发时钟信号选通的标志。 时钟信号的门控禁用执行数学运算的一个或多个处理级和/或器件。 禁用级和/或设备可以在减少的数据路径上计算数学运算的正确结果。 当设备被禁用时，可能会关闭设备电源，直到后续操作再次要求设备。
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公开(公告)号：US20100100578A1
公开(公告)日：2010-04-22
申请号：US12253713
申请日：2008-10-17
申请人： Son Trong Dao , Juergen Georg Haess , Michael Klaus Kroener , Silvia Melitta Mueller , Jochen Preiss
发明人： Son Trong Dao , Juergen Georg Haess , Michael Klaus Kroener , Silvia Melitta Mueller , Jochen Preiss
IPC分类号： G06F7/38
CPC分类号： G06F7/483
摘要： A distributed residue checking apparatus for a floating point unit having a plurality of functional elements performing floating-point operations on a plurality of operands. The distributed residue checking apparatus includes a plurality of residue generators which generate residue values for the operands and the functional elements, and a plurality of residue checking units distributed throughout the floating point unit. Each residue checking unit receives a first residue value and a second residue value from respective residue generators and compares the first residue value to the second residue value to determine whether an error has occurred in a floating-point operation performed by a respective functional element.
摘要翻译： 一种用于具有对多个操作数执行浮点运算的多个功能单元的浮点单元的分布式残留检查装置。 所述分布式残差检查装置包括生成所述操作数和所述功能元件的残差值的多个残差生成器，以及分布在所述浮点单元中的多个残差检查单元。 每个残差检查单元从相应的残差发生器接收第一残差值和第二残差值，并将第一残差值与第二残差值进行比较，以确定在由各个功能元件执行的浮点运算中是否发生了错误。
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公开(公告)号：US20100058266A1
公开(公告)日：2010-03-04
申请号：US12201092
申请日：2008-08-29
申请人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
发明人： Maarten Boersma , Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A 3-stack floorplan for a floating point unit includes: an aligner located in the center of the floating point unit; a frontend located directly above the aligner; a multiplier located directly below the frontend and next to the aligner; an adder located directly next to the multiplier and directly below the aligner; a normalizer located directly above the adder; and a rounder located directly above the normalizer.
摘要翻译： 用于浮点单元的三层平面布置图包括：位于浮点单元中心的对准器; 位于对准器正上方的前端; 位于前端正对着对准器旁边的乘数; 位于乘法器旁边并直接位于校准器下方的加法器; 位于加法器正上方的归一化器; 以及位于归一化器正上方的四舍五入。
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