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公开(公告)号：US20120284548A1
公开(公告)日：2012-11-08
申请号：US13552327
申请日：2012-07-18
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/3287 , G06F9/3001 , G06F9/30105 , G06F9/30192 , Y02D10/171
摘要： A method and system for reducing power consumption when processing mathematical operations. Power may be reduced in processor hardware devices that receive one or more operands from an execution unit that executes instructions. A circuit detects when at least one operand of multiple operands is a zero operand, prior to the operand being forwarded to an execution component for completing a mathematical operation. When at least one operand is a zero operand or at least one operand is “unordered”, a flag is set that triggers a gating of a clock signal. The gating of the clock signal disables one or more processing stages and/or devices, which perform the mathematical operation. Disabling the stages and/or devices enables computing the correct result of the mathematical operation on a reduced data path. When a device(s) is disabled, the device may be powered off until the device is again required by subsequent operations.
摘要翻译： 一种在处理数学运算时降低功耗的方法和系统。 在从执行指令的执行单元接收一个或多个操作数的处理器硬件设备中，功率可能会降低。 在将操作数转发到执行组件以完成数学运算之前，电路检测多个操作数的至少一个操作数是否为零操作数。 当至少一个操作数为零操作数或至少一个操作数无序时，会设置一个触发门控时钟信号的标志。 时钟信号的门控禁用执行数学运算的一个或多个处理级和/或器件。 禁用级和/或设备可以在减少的数据路径上计算数学运算的正确结果。 当设备被禁用时，可能会关闭设备电源，直到后续操作再次要求设备。
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公开(公告)号：US08578196B2
公开(公告)日：2013-11-05
申请号：US13552327
申请日：2012-07-18
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/3287 , G06F9/3001 , G06F9/30105 , G06F9/30192 , Y02D10/171
摘要： A method and system for reducing power consumption when processing mathematical operations. Power may be reduced in processor hardware devices that receive one or more operands from an execution unit that executes instructions. A circuit detects when at least one operand of multiple operands is a zero operand, prior to the operand being forwarded to an execution component for completing a mathematical operation. When at least one operand is a zero operand or at least one operand is “unordered”, a flag is set that triggers a gating of a clock signal. The gating of the clock signal disables one or more processing stages and/or devices, which perform the mathematical operation. Disabling the stages and/or devices enables computing the correct result of the mathematical operation on a reduced data path. When a device(s) is disabled, the device may be powered off until the device is again required by subsequent operations.
摘要翻译： 一种在处理数学运算时降低功耗的方法和系统。 在从执行指令的执行单元接收一个或多个操作数的处理器硬件设备中，功率可能会降低。 在将操作数转发到执行组件以完成数学运算之前，电路检测多个操作数的至少一个操作数是否为零操作数。 当至少一个操作数为零操作数或至少一个操作数为“无序”时，设置触发时钟信号选通的标志。 时钟信号的门控禁用执行数学运算的一个或多个处理级和/或器件。 禁用级和/或设备可以在减少的数据路径上计算数学运算的正确结果。 当设备被禁用时，可能会关闭设备电源，直到后续操作再次要求设备。
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公开(公告)号：US08255726B2
公开(公告)日：2012-08-28
申请号：US12176191
申请日：2008-07-18
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/3287 , G06F9/3001 , G06F9/30105 , G06F9/30192 , Y02D10/171
摘要： A method, system and computer program product for reducing power consumption when processing mathematical operations. Power may be reduced in processor hardware devices that receive one or more operands from an execution unit that executes instructions. A circuit detects when at least one operand of multiple operands is a zero operand, prior to the operand being forwarded to an execution component for completing a mathematical operation. When at least one operand is a zero operand or at least one operand is “unordered”, a flag is set that triggers a gating of a clock signal. The gating of the clock signal disables one or more processing stages and/or devices, which perform the mathematical operation. Disabling the stages and/or devices enables computing the correct result of the mathematical operation on a reduced data path. When a device(s) is disabled, the device may be powered off until the device is again required by subsequent operations.
摘要翻译： 一种用于在处理数学运算时降低功耗的方法，系统和计算机程序产品。 在从执行指令的执行单元接收一个或多个操作数的处理器硬件设备中，功率可能会降低。 在将操作数转发到执行组件以完成数学运算之前，电路检测多个操作数的至少一个操作数是否为零操作数。 当至少一个操作数为零操作数或至少一个操作数为“无序”时，设置触发时钟信号选通的标志。 时钟信号的门控禁用执行数学运算的一个或多个处理级和/或器件。 禁用级和/或设备可以在减少的数据路径上计算数学运算的正确结果。 当设备被禁用时，可能会关闭设备电源，直到后续操作再次要求设备。
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公开(公告)号：US20090198758A1
公开(公告)日：2009-08-06
申请号：US12023072
申请日：2008-01-31
IPC分类号： G06F7/496
CPC分类号： G06F7/49994 , G06F7/523 , G06F7/5318 , G06F7/5332 , G06F7/5443
摘要： A method for implementing sign extension within a multi-precision multiplier is described. The method includes receiving a first input within a multiplier core of the multiplier, receiving a second input within the multiplier core, and creating partial products in the multiplier core using the first and second inputs. The method also includes summing up the partial products in a partial product reduction tree in the multiplier core. The method also includes performing sign extension within the partial product reduction tree of the multiplier core by adding a value to a partial product of the partial product reduction tree. The method further includes computing an output from the partial product reduction tree, the output including a final product of the first and second inputs signed extended to a desired width.
摘要翻译： 描述了一种在多精度乘法器内实现符号扩展的方法。 该方法包括：在乘法器的乘法器核心内接收第一输入，接收乘法器内核中的第二输入，以及使用第一和第二输入在乘法器内核中产生部分乘积。 该方法还包括在乘法器核心中的部分乘积减少树中总结部分乘积。 该方法还包括通过向部分乘积减少树的部分乘积添加值来在乘法器核心的部分乘积减少树内执行符号扩展。 该方法还包括计算来自部分乘积减少树的输出，该输出包括被扩展到期望宽度的第一和第二输入的最终产品。
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5.发明申请METHODS FOR CONFLICT-FREE, COOPERATIVE EXECUTION OF COMPUTATIONAL PRIMITIVES ON MULTIPLE EXECUTION UNITS 失效无冲突的方法，多个执行单位的计算原则的合作执行公开(公告)号：US20090198974A1
公开(公告)日：2009-08-06
申请号：US12023432
申请日：2008-01-31
CPC分类号： G06F7/57 , G06F7/49921 , G06F9/30014 , G06F9/3893
摘要： A method for executing multiple computational primitives is provided in accordance with exemplary embodiments. A first computational unit and at least a second computational unit cooperate to execute multiple computational primitives. The first computational unit independently computes other computational primitives. By virtue of arbitration for shared source operand buses or shared result buses, availability of the first and second computational units needed to execute cooperatively the multiple computational primitives is assured by a process of reservation as used for a computational primitive executed on a dedicated computational unit.
摘要翻译： 根据示例性实施例提供了一种用于执行多个计算原语的方法。 第一计算单元和至少第二计算单元合作执行多个计算原语。 第一计算单元独立计算其他计算原语。 通过对共享源操作数总线或共享结果总线的仲裁，通过协作地执行多个计算原语所需的第一和第二计算单元的可用性通过用于在专用计算单元上执行的计算原语的预留处理来确保。
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6.发明授权Multiplexing output from second execution unit add/saturation processing portion of wider width intermediate result of first primitive execution unit for compound computation 失效来自第二执行单元的多路复用输出用于复合计算的第一原始执行单元的较宽宽度中间结果的添加/饱和处理部分公开(公告)号：US07694112B2
公开(公告)日：2010-04-06
申请号：US12023432
申请日：2008-01-31
IPC分类号： G06F9/302
CPC分类号： G06F7/57 , G06F7/49921 , G06F9/30014 , G06F9/3893
摘要： A method for executing multiple computational primitives is provided in accordance with exemplary embodiments. A first computational unit and at least a second computational unit cooperate to execute multiple computational primitives. The first computational unit independently computes other computational primitives. By virtue of arbitration for shared source operand buses or shared result buses, availability of the first and second computational units needed to execute cooperatively the multiple computational primitives is assured by a process of reservation as used for a computational primitive executed on a dedicated computational unit.
摘要翻译： 根据示例性实施例提供了一种用于执行多个计算原语的方法。 第一计算单元和至少第二计算单元合作执行多个计算原语。 第一计算单元独立计算其他计算原语。 通过对共享源操作数总线或共享结果总线的仲裁，通过协作地执行多个计算原语所需的第一和第二计算单元的可用性通过用于在专用计算单元上执行的计算原语的预留处理来确保。
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7.发明授权Integrated circuit with stacked computational units and configurable through vias 失效具有堆叠计算单元并可通过通孔进行配置的集成电路公开(公告)号：US08421500B2
公开(公告)日：2013-04-16
申请号：US12952365
申请日：2010-11-23
申请人： Harry S. Barowski , Tim Niggemeier
发明人： Harry S. Barowski , Tim Niggemeier
IPC分类号： H03K19/177
CPC分类号： G06F15/80 , G06F15/7842 , H01L22/22 , H01L23/544 , H01L25/0657 , H01L2223/54433 , H01L2223/5444 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： A technique for manufacturing a three-dimensional integrated circuit includes stacking a memory unit on a first die that includes a first computational unit. In this case, the memory unit is included in a second die. A second computational unit that is included in a third die is stacked on the second die. Sets of vertical vias that extend through the first, second, and third dies are connected to connect components of the first and second computational units and the memory unit. Multiplexers of the first and second computational units are configured to selectively couple the components to different ones of the sets of vertical vias responsive to respective control words for each of the first and third dies.
摘要翻译： 一种用于制造三维集成电路的技术包括在包括第一计算单元的第一管芯上堆叠存储器单元。 在这种情况下，存储器单元包括在第二管芯中。 包括在第三管芯中的第二计算单元堆叠在第二管芯上。 连接穿过第一，第二和第三管芯的垂直通孔的连接件连接到第一和第二计算单元和存储器单元的部件。 第一和第二计算单元的多路复用器被配置为响应于用于第一和第三管芯中的每一个的相应控制字选择性地将组件耦合到垂直通孔中的不同组。
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公开(公告)号：US07509511B1
公开(公告)日：2009-03-24
申请号：US12116085
申请日：2008-05-06
IPC分类号： G06F1/32
CPC分类号： G06F1/3275 , G06F1/3228 , G06F1/3287 , G06F9/30123 , G06F9/30141 , G06F9/384 , G06F9/3851 , Y02D10/14 , Y02D10/171
摘要： A method for reducing leakage current within a register file of a processor is disclosed. The register file within the processor is partitioned into at least two power domains, and each of the two power domains can be powered independently. At least one of the two power domains includes at least as many physical registers as there are architected registers defined in an instruction set architecture of the processor. In response to an occurrence of an idle condition within the processor, all architected register file entries are consolidated into one of power domains that will not be powered off, and the power domains that does not contain any architected register file entries after consolidating are powered off. Afterwards, in response to a detection of an end of the idle condition, all of the power domains are powered back on.
摘要翻译： 公开了一种用于减少处理器的寄存器文件内的泄漏电流的方法。 处理器内的寄存器文件被划分为至少两个电源域，并且两个电源域中的每一个可以独立供电。 两个功率域中的至少一个包括至少与处理器的指令集架构中定义的架构寄存器一样多的物理寄存器。 为了响应处理器内的空闲状况的发生，所有架构的寄存器文件条目被合并到不被关闭的电源域之一中，并且在合并之后不包含任何架构化的寄存器文件条目的电源被关闭 。 之后，响应于空闲状态的结束的检测，所有的电源域被重新接通。
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9.发明申请Integrated Circuit with Stacked Computational Units and Configurable through Vias 失效具有堆叠计算单元的集成电路和通过通道可配置公开(公告)号：US20110131391A1
公开(公告)日：2011-06-02
申请号：US12952365
申请日：2010-11-23
申请人： Harry S. Barowski , Tim Niggemeier
发明人： Harry S. Barowski , Tim Niggemeier
CPC分类号： G06F15/80 , G06F15/7842 , H01L22/22 , H01L23/544 , H01L25/0657 , H01L2223/54433 , H01L2223/5444 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： A technique for manufacturing a three-dimensional integrated circuit includes stacking a memory unit on a first die that includes a first computational unit. In this case, the memory unit is included in a second die. A second computational unit that is included in a third die is stacked on the second die. Sets of vertical vias that extend through the first, second, and third dies are connected to connect components of the first and second computational units and the memory unit. Multiplexers of the first and second computational units are configured to selectively couple the components to different ones of the sets of vertical vias responsive to respective control words for each of the first and third dies.
摘要翻译： 一种用于制造三维集成电路的技术包括在包括第一计算单元的第一管芯上堆叠存储器单元。 在这种情况下，存储器单元包括在第二管芯中。 包括在第三管芯中的第二计算单元堆叠在第二管芯上。 连接穿过第一，第二和第三管芯的垂直通孔的连接件连接到第一和第二计算单元和存储器单元的部件。 第一和第二计算单元的多路复用器被配置为响应于用于第一和第三管芯中的每一个的相应控制字选择性地将组件耦合到垂直通孔中的不同组。
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