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公开(公告)号：US20130332501A1
公开(公告)日：2013-12-12
申请号：US13493002
申请日：2012-06-11
CPC分类号： G06F7/483 , G06F7/509 , G06F7/5324 , G06F7/5332 , G06F7/5443
摘要： A fused multiply-adder is disclosed. The fused multiply-adder includes a Booth encoder, a fraction multiplier, a carry corrector, and an adder. The Booth encoder initially encodes a first operand. The fraction multiplier multiplies the Booth-encoded first operand by a second operand to produce partial products, and then reduces the partial products into a set of redundant sum and carry vectors. The carry corrector then generates a carry correction factor for correcting the carry vectors. The adder adds the redundant sum and carry vectors and the carry correction factor to a third operand to yield a final result.
摘要翻译： 公开了一种融合乘法器。 融合乘法加法器包括布斯编码器，分数乘法器，进位校正器和加法器。 Booth编码器最初编码第一个操作数。 分数乘法器将布斯特编码的第一操作数乘以第二操作数以产生部分乘积，然后将部分乘积减少为一组冗余和和携带向量。 进位校正器然后产生用于校正进位矢量的进位校正因子。 加法器将冗余和并将载入和进位校正因子加到第三个操作数，以产生最终结果。
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2.发明授权Advanced execution of extended floating-point add operations in a narrow dataflow 失效在窄数据流中高级执行扩展浮点添加操作公开(公告)号：US07373369B2
公开(公告)日：2008-05-13
申请号：US10861151
申请日：2004-06-04
IPC分类号： G06F7/38
CPC分类号： G06F7/485 , G06F2207/3896
摘要： A method and system for performing floating point additive arithmetic operations of long operands in a narrow dataflow. The operands include first and second floating point numbers having first and second mantissas, respectively, the second operand greater than the first operand. The mantissas are both separated into a low portion and a high portion, the high portions are loaded into N-bit operand registers. The high portion of the first mantissa is aligned with respect to the high portion of the second mantissa, the high portions are then moved into 2N-bit registers. The low portion of the first mantissa is aligned in accordance with the alignment of the first mantissa high portion. The low portions of both mantissas are then concatenated into the registers, the first mantissa concatenated using a hold-function circuit. A 2N-bit-wide adder performs the additive arithmetic operation on the concatenated mantissas.
摘要翻译： 一种用于在窄数据流中执行长操作数的浮点加法运算的方法和系统。 操作数分别包括具有第一和第二尾数的第一和第二浮点数，第二操作数大于第一操作数。 尾数分为低部分和高部分，高部分被装载到N位操作数寄存器中。 第一尾数的高部分相对于第二尾数的高部分排列，然后将高部分移动到2N位寄存器中。 第一尾数的低部分根据第一尾数高部分的对准来对齐。 两个尾数的低部分然后连接到寄存器中，第一个尾数使用保持功能电路连接。 2N位宽的加法器对级联尾数进行加法运算。
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公开(公告)号：US07716266B2
公开(公告)日：2010-05-11
申请号：US11341256
申请日：2006-01-26
CPC分类号： G06F7/483 , G06F7/5443 , G06F2207/3812
摘要： A method and system for performing a binary mode and hexadecimal mode Multiply-Add floating point operation in a floating point arithmetic unit according to a formula A*C+B, wherein A, B and C operands each have a fraction and an exponent part expA, expB and expC and the exponent of the product A*C is calculated and compared to the exponent of the addend under inclusion of an exponent bias value dedicated to use unsigned biased exponents, wherein the comparison yields a shift amount used for aligning the addend with the product operand, wherein a shift amount calculation provides a common value CV for both binary and hexadecimal according to the formula (expA+expC−expB+CV).
摘要翻译： 一种用于执行二进制模式和十六进制模式的方法和系统根据公式A * C + B在浮点算术单元中乘法 - 浮点运算，其中A，B和C操作数各自具有分数和指数部分expA ，expB和expC和乘积A * C的指数被计算，并且与包含专用于使用无符号偏移指数的指数偏差值的加数指数进行比较，其中比较产生用于将加数与 产品操作数，其中移位量计算根据公式（expA + expC-expB + CV）为二进制和十六进制提供公共值CV。
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公开(公告)号：US09122517B2
公开(公告)日：2015-09-01
申请号：US13493002
申请日：2012-06-11
CPC分类号： G06F7/483 , G06F7/509 , G06F7/5324 , G06F7/5332 , G06F7/5443
摘要： A fused multiply-adder is disclosed. The fused multiply-adder includes a Booth encoder, a fraction multiplier, a carry corrector, and an adder. The Booth encoder initially encodes a first operand. The fraction multiplier multiplies the Booth-encoded first operand by a second operand to produce partial products, and then reduces the partial products into a set of redundant sum and carry vectors. The carry corrector then generates a carry correction factor for correcting the carry vectors. The adder adds the redundant sum and carry vectors and the carry correction factor to a third operand to yield a final result.
摘要翻译： 公开了一种融合乘法器。 融合乘法加法器包括布斯编码器，分数乘法器，进位校正器和加法器。 Booth编码器最初编码第一个操作数。 分数乘法器将布斯特编码的第一操作数乘以第二操作数以产生部分乘积，然后将部分乘积减少为一组冗余和和携带向量。 进位校正器然后产生用于校正进位矢量的进位校正因子。 加法器将冗余和并将载入和进位校正因子加到第三个操作数，以产生最终结果。
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5.发明授权Method and floating point unit to convert a hexadecimal floating point number to a binary floating point number 失效方法和浮点单位将十六进制浮点数转换为二进制浮点数公开(公告)号：US07840622B2
公开(公告)日：2010-11-23
申请号：US11489920
申请日：2006-07-20
CPC分类号： H03M7/24
摘要： Method to convert a hexadecimal floating point number (H) into a binary floating point number by using a Floating Point Unit (FPU) with fused multiply add with an A-register a B-register for two multiplicand operands and a C-register for an addend operand, wherein a leading zero counting unit (LZC) is associated to the addend C-register, wherein the difference of the leading zero result provided by the LZC and the input exponent (E) is calculated by a control unit and determines based on the Raw-Result-Exponent a force signal (F) with special conditions like ‘Exponent Overflow’, ‘Exponent Underflow’, and ‘Zero Result’.
摘要翻译： 通过使用具有融合乘法的浮点单元（FPU）将十六进制浮点数（H）转换为二进制浮点数的方法，将A寄存器用于两个被乘数操作数的B寄存器和用于 加法操作数，其中前置零计数单元（LZC）与加数C寄存器相关联，其中由LZC提供的前导零结果和输入指数（E）的差异由控制单元计算并基于 原始结果指数具有特殊条件（如“指数溢出”，“指数下溢”和“零结果”）的力信号（F）。
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6.发明授权Floating point unit with fused multiply add and method for calculating a result with a floating point unit 失效具有融合乘法的浮点单元和用浮点单元计算结果的方法公开(公告)号：US07461117B2
公开(公告)日：2008-12-02
申请号：US11055812
申请日：2005-02-11
申请人： Son Dao Trong , Juergen Haess , Christian Jacobi , Klaus Michael Kroener , Silvia Melitta Mueller , Jochen Preiss
发明人： Son Dao Trong , Juergen Haess , Christian Jacobi , Klaus Michael Kroener , Silvia Melitta Mueller , Jochen Preiss
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/5443
摘要： The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with an alignment logic (3) which uses the alignment shift amount to align the fraction (fb) of the addend operand, with a multiply logic (4) which multiplies the fractions of the multiplicand operands (fa, fc), with a adder logic (5) which adds the outputs of the alignment logic (3) and the multiply logic (4), with a normalization logic (6) which normalizes the output of the adder logic (5), which is characterized in that a leading zero logic (7) is provided which computes the number of leading zeros of the fraction of the addend operand (fb), and that a compare logic (8) is provided which based on the number of leading zeros and the alignment shift amount computes select signals that indicate whether the most significant bits of the alignment logic (3) output have all the same value in order to: a) control the carry logic of the adder logic (5) and/or b) control a stage of the normalization logic (6).
摘要翻译： 本发明提出了一种具有融合乘法运算的浮点单元（1），具有一个加数运算数（eb，fb）和两个被乘数运算符（ea，fa; ec，fc），其中移位量逻辑（2）基于 操作数（ea，eb和ec）的指数利用对准逻辑（3）计算对准偏移量，该对准逻辑（3）使用对准移位量来对齐加数操作数的分数（fb）与乘法逻辑（4） 将乘法器操作数（fa，fc）的分数与加法器逻辑（5）相乘，该逻辑（5）将对准逻辑（3）和乘法逻辑（4）的输出与归一化逻辑（6）进行归一化，归一化逻辑（6） 加法器逻辑（5）的特征在于提供一个前导零逻辑（7），其计算加法运算数（fb）的分数的前导零的数量，并且提供比较逻辑（8） 其基于前导零的数量和对准偏移量计算指示mo的选择信号 对准逻辑（3）输出的高有效位具有全部相同的值，以便：a）控制加法器逻辑（5）的进位逻辑和/或b）控制归一化逻辑（6）的阶段。
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公开(公告)号：US07392273B2
公开(公告)日：2008-06-24
申请号：US10732039
申请日：2003-12-10
CPC分类号： G06F7/483 , G06F5/012 , G06F7/5443
摘要： Arithmetic processing circuits in a circuit in a floating point processor having a fused multiply/ADD circuitry. In order to avoid waiting cycles in the normalizer of the floating point arithmetic, control logic calculates in an extremely early state of the overall Multiply/Add processing. Parts of the intermediate add result are significant and have to be selected in the pre-normalizer multiplexer to be fed to the normalizer by counting the leading zero bits (LAB) of the addend in a dedicated circuit right at the beginning of the pipe. LAB is added to the shift amount (SA) that is calculated to align the addend and is then compared with the width of the incrementer. If the sum of (SA+LAB) is larger than the width of the incrementer, which is a constant value, then no significant bits are in the high-part of the intermediate result, and the pre-normalizer multiplexer selects the data from a second predetermined position, otherwise from a first predetermined position.
摘要翻译： 具有融合乘法/ ADD电路的浮点处理器中的电路中的算术处理电路。 为了避免浮点运算的归一化器中的等待周期，控制逻辑在整体乘法/加法处理的极早期状态下进行计算。 中间加法结果的部分是重要的，必须在预归一化器多路复用器中选择，以通过在管道开头右侧的专用电路中的加数的前导零比特（LAB）进行计数来馈送到归一化器。 将LAB加到被计算以对齐加数的移位量（SA），然后与增量器的宽度进行比较。 如果（SA + LAB）的和大于作为常数值的增量器的宽度，则中间结果的高部分中没有有效位，并且预标准化器多路复用器选择来自 第二预定位置，否则从第一预定位置。
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