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    Method of time multiplexing a programmable logic device
    11.
    发明授权
    Method of time multiplexing a programmable logic device 失效
    时间复用可编程逻辑器件的方法

    公开(公告)号：US5629637A

    公开(公告)日：1997-05-13

    申请号：US517017

    申请日：1995-08-18

    申请人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert A. Johnson ,  Jennifer Wong

    发明人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert A. Johnson ,  Jennifer Wong

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17752 ,  H03K19/17704 ,  H03K19/17756

    摘要： A method of time multiplexing a programmable logic device (PLD) includes inputting a design for the PLD and dividing an evaluation of the logic of the design into a plurality of micro cycles. The method further includes identifying the logic not within a critical path of the design and rescheduling the identified logic for evaluation in other micro cycles. Alternatively, if the PLD includes a plurality of combinational logic elements, the method further includes scheduling a combinational logic element in a micro cycle no earlier than all the combinational logic elements that generate the input signals to said combinational logic element. Further alternatively, if the PLD includes a plurality of combinational logic elements and a plurality of sequential logic elements, the method further includes scheduling a sequential logic element in a micro cycle no earlier than all the combinational logic elements that generate input signals to the sequential logic element and scheduling each sequential logic element in a micro cycle no earlier than all the combinational logic elements or the sequential logic elements that the sequential logic element drives. If the PLD includes a plurality of combinational logic elements, a plurality of sequential logic elements, and a storage device, the method further includes mapping at least one of the sequential logic elements in the design into the storage device and scheduling the plurality of combinational logic elements and the remaining sequential logic elements.

    摘要翻译： 一种时间复用可编程逻辑器件（PLD）的方法包括输入PLD的设计并将设计逻辑的评估分成多个微循环。 该方法还包括识别不在设计的关键路径内的逻辑，并重新安排所识别的逻辑以在其它微循环中进行评估。 或者，如果PLD包括多个组合逻辑元件，则该方法还包括在不早于生成到所述组合逻辑元件的输入信号的所有组合逻辑元件的微循环中调度组合逻辑元件。 此外，如果PLD包括多个组合逻辑元件和多个顺序逻辑元件，则该方法还包括在不早于生成到顺序逻辑的输入信号的所有组合逻辑元件的微循环中调度顺序逻辑元件 元素，并且在不超过所有组合逻辑元件或顺序逻辑元件驱动的顺序逻辑元件的微循环中调度每个顺序逻辑元件。 如果PLD包括多个组合逻辑元件，多个顺序逻辑元件和存储装置，则该方法还包括将设计中的顺序逻辑元件中的至少一个映射到存储装置中并调度多个组合逻辑 元素和剩余的顺序逻辑元素。

    Combination Local Delivery Using a Stent
    17.
    发明申请
    Combination Local Delivery Using a Stent 审中-公开
    组合使用支架本地交付

    公开(公告)号：US20100092534A1

    公开(公告)日：2010-04-15

    申请号：US12249576

    申请日：2008-10-10

    申请人： Ayala Hezi-Yamit ,  Iskender Matt Bilge ,  Jennifer Wong ,  Carol Sullivan ,  Natividad Vasquez

    发明人： Ayala Hezi-Yamit ,  Iskender Matt Bilge ,  Jennifer Wong ,  Carol Sullivan ,  Natividad Vasquez

    IPC分类号： A61F2/04 ,  A61K31/58 ,  A61K31/4355

    CPC分类号： A61L31/10 ,  A61L31/16 ,  A61L2300/222 ,  A61L2300/416 ,  A61L2300/45

    摘要： Described herein are implantable medical devices useful in treating vascular conditions such as restenosis. In one embodiment, stents are described in which a combination of bioactive agents is described for local delivery in the vasculature. The combination of bioactive agents comprises at least one compound capable of inhibiting smooth muscle cell proliferation and at least one compound capable of mitigating MCP- and/or TF induction. For example, a compound capable of inhibiting smooth muscle cell proliferation is a mTOR inhibitor and a compound capable of mitigating MCP-1 and/or TF induction is a corticosteroid.

    摘要翻译： 本文描述了可用于治疗诸如再狭窄的血管病变的可植入医疗装置。 在一个实施方案中，描述了支架，其中描述了生物活性剂的组合用于脉管系统中的局部递送。 生物活性剂的组合包含至少一种能够抑制平滑肌细胞增殖的化合物和至少一种能够减轻MCP-和/或TF诱导的化合物。 例如，能够抑制平滑肌细胞增殖的化合物是mTOR抑制剂，能够缓解MCP-1和/或TF诱导的化合物是皮质类固醇。

    Arithmetic circuit with multiplexed addend inputs
    18.
    发明授权
    Arithmetic circuit with multiplexed addend inputs 有权
    具有复用加法输入的算术电路

    公开(公告)号：US07480690B2

    公开(公告)日：2009-01-20

    申请号：US11019854

    申请日：2004-12-21

    申请人： James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

    发明人： James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

    IPC分类号： G06F7/48

    CPC分类号： G06F7/509

    摘要： Described are arithmetic circuits divided logically into a product generator and an adder. Multiplexing circuitry logically disposed between the product generator and the adder supports conventional functionality by providing partial products from the product generator to addend terminals of the adder. The multiplexing circuitry can also be controlled to direct a number of external added inputs to the adder. The additional addend inputs can include inputs and outputs cascaded from other arithmetic circuits.

    摘要翻译： 描述的是算术电路，逻辑上分为乘积发生器和加法器。 逻辑上位于产品发生器和加法器之间的多路复用电路通过提供来自产品发生器的部分乘积到加法器的末端来支持常规功能。 还可以控制复用电路以将多个外部添加的输入引导到加法器。 附加加数输入可以包括从其他算术电路级联的输入和输出。

    Mathematical circuit with dynamic rounding
    19.
    发明授权
    Mathematical circuit with dynamic rounding 有权
    具有动态四舍五入的数学电路

    公开(公告)号：US07467177B2

    公开(公告)日：2008-12-16

    申请号：US11019853

    申请日：2004-12-21

    申请人： James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

    发明人： James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

    IPC分类号： G06F7/38

    CPC分类号： G06F7/49963

    摘要： Described are mathematical circuits that perform flexible rounding schemes. The circuits require few additional resources and can be adjusted dynamically to change the number of bits involved in the rounding. In one embodiment, a DSP circuit stores a rounding constant selected from the group of binary numbers 2(M−1) and 2(M−1)−1, calculates a correction factor, and sums the rounding constant, the correction factor, and a data item to obtain a rounded data item.

    摘要翻译： 描述了执行灵活舍入方案的数学电路。 这些电路需要很少的额外资源，并且可以动态调整以改变舍入所涉及的位数。 在一个实施例中，DSP电路存储从二进制数2（M-1）和2（M-1）-1组中选择的舍入常数，计算校正因子，并将舍入常数，校正因子和 一个数据项以获得舍入的数据项。