公开(公告)号：US07349508B2

公开(公告)日：2008-03-25

申请号：US10714202

申请日：2003-11-14

申请人： Thomas Duda ,  Lajos Gaszi ,  Peter Gregorius ,  Torsten Hinz ,  Martin Renner

发明人： Thomas Duda ,  Lajos Gaszi ,  Peter Gregorius ,  Torsten Hinz ,  Martin Renner

IPC分类号： H04L7/00

CPC分类号： H04L25/03885

摘要： A method and a device for reconstructing data, clocked at a symbol rate, from a signal which has been distorted by transmission of a transmission link, are disclosed. The method or respectively, the device, being predominantly performed or implemented, respectively, by means of digital circuit technology in order to improve the quality of the data recovery. The method includes amplifying the signal amplitude attenuated by the transmission; filtering high-frequency interference frequencies above the symbol rate; discretizing the analog signal by means of an analog/digital converter; performing a cable approximation by means of a digitally implemented cable approximation filter in order to obtain an equalized signal; and recovering the data from the equalized signal by means of a phase-locked loop.

摘要翻译： 公开了一种用于通过传输链路传输已被失真的信号重建以符号速率计时的数据的方法和装置。 该方法或分别主要通过数字电路技术执行或实现的装置，以便提高数据恢复的质量。 该方法包括放大由传输衰减的信号幅度; 过滤高于符号率的高频干扰频率; 通过模拟/数字转换器离散模拟信号; 通过数字实现的电缆近似滤波器执行电缆近似，以获得均衡的信号; 并通过锁相环从均衡信号中恢复数据。

公开(公告)号：US07088976B2

公开(公告)日：2006-08-08

申请号：US10492390

申请日：2002-09-04

申请人： Peter Gregorius ,  Torsten Hinz

发明人： Peter Gregorius ,  Torsten Hinz

IPC分类号： H04B1/06 ,  H04B7/00

CPC分类号： H04L7/033 ,  H04L7/0083

摘要： In a transceiver which is configured in particular for transmitting optical data, there is provided a device for reconstructing data from a received data signal (RX), having a clock-signal recovery unit (3) for recovering a clock signal belonging to the transmitted data from the received data signal, and having a data reconstruction unit (2) for reconstructing the transmitted data from the received data signal using the recovered clock signal (fCLK), and for emitting a data stream (DATA) which is synchronised with the recovered clock signal. A detector unit (9) detects an error state in the received data signal (RX) which prevents the data from being reconstructed reliably, switching means having a digital phase-locked lock (13) being provided to enable a signal having a clock rate which corresponds to the mean value of the clock signal (fCLK) previously recovered by the clock-signal recovery unit (3) to be fed, as a reference signal, to a phase-locked loop of the clock-signal recovery unit (3) in this event in place of the received data signal, thus ensuring that the phase-locked loop of the clock-signal recovery unit (3) will continue to oscillate properly even in this event.

摘要翻译： 在特别用于发送光数据的收发器中，提供了一种用于从接收的数据信号（RX）重建数据的装置，具有用于恢复属于发送数据的时钟信号的时钟信号恢复单元（3） 并且具有数据重建单元（2），用于使用恢复的时钟信号（f CLK）从接收到的数据信号重建发送的数据，并且用于发射数据流（DATA ）与恢复的时钟信号同步。 检测器单元（9）检测接收到的数据信号（RX）中的错误状态，其阻止数据被可靠地重建，具有数字锁相锁（13）的开关装置被提供以使得具有时钟速率的信号 对应于由时钟信号恢复单元（3）预先恢复的作为参考信号的时钟信号（f CLK）的平均值到时钟的锁相环 在这种情况下，信号恢复单元（3）代替接收到的数据信号，从而确保即使在这种情况下时钟信号恢复单元（3）的锁相环仍将适当地振荡。

公开(公告)号：US08410963B2

公开(公告)日：2013-04-02

申请号：US13070293

申请日：2011-03-23

申请人： Torsten Hinz

发明人： Torsten Hinz

IPC分类号： H03M3/00

CPC分类号： H03M1/822 ,  H03F3/217 ,  H03H17/0283 ,  H03H17/04

摘要： In an embodiment, an oversampled data converter includes a lowpass filter having a filter stage comprising a dynamic limiter, where the dynamic limiter having a limit set by an signal level at an input to the oversampled data converter. The oversampled data converter also includes a quantizing block comprising an input coupled to an output of the lowpass filter and an output coupled to an input of the lowpass filter.

摘要翻译： 在一个实施例中，过采样数据转换器包括具有滤波器级的低通滤波器，该滤波器级包括动态限制器，其中动态限制器具有由过采样数据转换器的输入处的信号电平设置的限制。 过采样数据转换器还包括量化块，其包括耦合到低通滤波器的输出的输入和耦合到低通滤波器的输入的输出。

公开(公告)号：US08250436B2

公开(公告)日：2012-08-21

申请号：US13287488

申请日：2011-11-02

申请人： Torsten Hinz ,  Gerhard Risse

发明人： Torsten Hinz ,  Gerhard Risse

IPC分类号： G11C29/00 ,  G06F13/00

CPC分类号： G06F11/1044 ,  G06F11/1666 ,  G06F11/20 ,  G11C5/04 ,  G11C2029/0409

摘要： A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module.

摘要翻译： 存储器装置包括第一存储器模块和第二存储器模块。 要写入存储器装置的信息项目被写入第一存储器模块和第二存储器模块。 当读取时，借助于与第一地址不同的第二地址，通过第一地址或第二存储器模块从第一存储器模块读取信息项。 随后检查信息项是否有缺陷。 如果是这种情况，则从相应的其他存储器模块读取信息项。

公开(公告)号：US08078937B2

公开(公告)日：2011-12-13

申请号：US11740762

申请日：2007-04-26

申请人： Torsten Hinz ,  Gerhard Risse

发明人： Torsten Hinz ,  Gerhard Risse

IPC分类号： G11C29/00

CPC分类号： G06F11/1044 ,  G06F11/1666 ,  G06F11/20 ,  G11C5/04 ,  G11C2029/0409

摘要： A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module.

摘要翻译： 存储器装置包括第一存储器模块和第二存储器模块。 要写入存储器装置的信息项目被写入第一存储器模块和第二存储器模块。 当读取时，借助于与第一地址不同的第二地址，通过第一地址或第二存储器模块从第一存储器模块读取信息项。 随后检查信息项是否有缺陷。 如果是这种情况，则从相应的其他存储器模块读取信息项。

公开(公告)号：US20090267654A1

公开(公告)日：2009-10-29

申请号：US12108351

申请日：2008-04-23

申请人： Torsten Hinz ,  Daniele Gardellini

发明人： Torsten Hinz ,  Daniele Gardellini

IPC分类号： H03K3/00

CPC分类号： H04L25/0278 ,  H04L25/0274 ,  H04L25/028

摘要： The invention relates to a line driver to drive a transmission line with a differentially balanced signal, with selectable signal amplitude, with output impedance matched to a characteristic impedance of the transmission line, and with reduced dissipation. The line driver includes a first driver subcircuit including a first and a second group of resistors. To drive an output node with a first signal sense, the first group of resistors is selectively coupled to a first bias voltage terminal and the second group to a second bias voltage terminal. To drive the first output node with a second signal sense, the first and second groups of resistors are both selectively coupled to the second bias voltage terminal. The line driver includes a second driver subcircuit. The second driver subcircuit includes a third and fourth group of resistors that are correspondingly switched.

摘要翻译： 本发明涉及一种线驱动器，其用具有可选择的信号幅度的差分平衡信号来驱动传输线，输出阻抗与传输线的特性阻抗匹配，并且具有减小的耗散。 线路驱动器包括包括第一和第二组电阻器的第一驱动器子电路。 为了驱动具有第一信号感测的输出节点，第一组电阻器被选择性地耦合到第一偏置电压端子，而第二组被选择性地耦合到第二偏置电压端子。 为了以第二信号感测驱动第一输出节点，第一和第二组电阻器都选择性地耦合到第二偏置电压端子。 线路驱动器包括第二驱动器子电路。 第二驱动器分支电路包括相应地切换的第三组和第四组电阻器。

公开(公告)号：US07194045B2

公开(公告)日：2007-03-20

申请号：US10477137

申请日：2002-05-08

申请人： Thomas Duda ,  Torsten Hinz ,  Martin Renner

发明人： Thomas Duda ,  Torsten Hinz ,  Martin Renner

IPC分类号： H04L27/00 ,  H04L7/00

CPC分类号： H04L7/033

摘要： The invention provides a method for recovering a digital datastream, in which a reference clock phase is recovered from the digital datastream, the digital datastream being received in a datastream receiver, low-pass filtered in a low-pass filter device, an edge position signal being determined by comparing an amplitude of the low-pass filtered datastream with a predetermined threshold value in an edge position detection device and a phase deviation being determined from a time difference between a 0/1 threshold intersection point of the threshold value with a 0/1 data transition or a −1/1 threshold intersection point of the threshold value with a −1/1 data transmission and the target time of the control system in a phase correction device, so that the phase deviation can be corrected with the phase correction offset in the phase correction device.

摘要翻译： 本发明提供一种恢复数字数据流的方法，其中从数字数据流中恢复参考时钟相位，在数据流接收机中接收数字数据流，在低通滤波器装置中低通滤波，边缘位置信号 通过将边缘位置检测装置中的低通滤波数据流的幅度与预定阈值进行比较来确定，并且相位偏差由阈值的0/1阈值交点之间的时间差与0 / 1数据转换或阈值相交点-1 -1数据传输和控制系统在相位校正装置中的目标时间，从而可以用相位校正校正相位偏差 在相位校正装置中偏移。

公开(公告)号：US08917875B2

公开(公告)日：2014-12-23

申请号：US13248346

申请日：2011-09-29

申请人： Christoph Braun ,  Thomas Duda ,  Torsten Hinz

发明人： Christoph Braun ,  Thomas Duda ,  Torsten Hinz

IPC分类号： H04R5/00 ,  H04S5/00

CPC分类号： H04S5/00 ,  H04S2400/07

摘要： A circuit for operating loudspeakers includes a first, second, third and fourth loudspeaker circuit, having one input each for injecting a signal and one output each for connecting a loudspeaker input. The loudspeaker circuits are designed to amplify the injected signal and to provide the amplified signal at the outputs thereof. The loudspeaker circuits can, for example, be used for a 2.1 sound system. The three channels for a 2.1 sound system can be implemented by an amplifier circuit with four loudspeaker circuits, one loudspeaker circuit each being required for the two stereo channels left and right. A subwoofer channel can be driven differentially by two loudspeaker circuits. The stereo channels are, by contrast, only still connected to one loudspeaker circuit each, and so the stereo channels require at least one further common ground cable.

摘要翻译： 用于操作扬声器的电路包括第一，第二，第三和第四扬声器电路，每个扬声器电路具有一个输入，每个用于注入信号，每个输入用于连接扬声器输入。 扬声器电路被设计成放大注入的信号并在其输出处提供放大的信号。 扬声器电路可以例如用于2.1声音系统。 一个2.1声道系统的三个通道可以由具有四个扬声器电路的放大器电路实现，一个扬声器电路需要两个立体声通道左右。 低音炮通道可以通过两个扬声器电路进行差分驱动。 相比之下，立体声通道每个仍然连接到一个扬声器电路，因此立体声通道需要至少一个另外的公共接地电缆。

公开(公告)号：US08321652B2

公开(公告)日：2012-11-27

申请号：US12184837

申请日：2008-08-01

申请人： Torsten Hinz

发明人： Torsten Hinz

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/7201

摘要： An embodiment of the invention relates to a mass storage device including a nonvolatile memory device with a plurality of memory management blocks and an address translation table formed with pointers to locations of the memory management blocks. A volatile memory device is included with an address index table formed with pointers to the pointers to the locations of the memory management blocks. The address index table is stored in the nonvolatile memory upon loss of bias voltage. Changes to the address translation table are accumulated in the volatile memory and written to the address translation table when at least a minimum quantity of the changes has been accumulated. The changes to the logical block address translation table accumulated in the volatile memory are written to a page in the address translation table after prior data in the page has been updated, written to another page, and then erased.

摘要翻译： 本发明的实施例涉及包括具有多个存储器管理块的非易失性存储器件和形成有指向存储器管理块的位置的地址转换表的大容量存储器件。 易失性存储器件包括地址索引表，该地址索引表由指向存储器管理块的位置的指针形成。 当偏置电压丢失时，地址索引表存储在非易失性存储器中。 当至少已经累积了最小量的变化时，地址转换表的变化被累积在易失性存储器中并写入地址转换表。 累积在易失性存储器中的逻辑块地址转换表的改变在页面中的先前数据被更新，被写入另一个页面之后被写入地址转换表中的页面，然后被擦除。

公开(公告)号：US07888975B2

公开(公告)日：2011-02-15

申请号：US12108351

申请日：2008-04-23

申请人： Torsten Hinz ,  Daniele Gardellini

发明人： Torsten Hinz ,  Daniele Gardellini

IPC分类号： H03B1/00 ,  H03K3/00

CPC分类号： H04L25/0278 ,  H04L25/0274 ,  H04L25/028

摘要： The invention relates to a line driver to drive a transmission line with a differentially balanced signal, with selectable signal amplitude, with output impedance matched to a characteristic impedance of the transmission line, and with reduced dissipation. The line driver includes a first driver subcircuit including a first and a second group of resistors. To drive an output node with a first signal sense, the first group of resistors is selectively coupled to a first bias voltage terminal and the second group to a second bias voltage terminal. To drive the first output node with a second signal sense, the first and second groups of resistors are both selectively coupled to the second bias voltage terminal. The line driver includes a second driver subcircuit. The second driver subcircuit includes a third and fourth group of resistors that are correspondingly switched.

摘要翻译： 本发明涉及一种线驱动器，其用具有可选择的信号幅度的差分平衡信号来驱动传输线，输出阻抗与传输线的特性阻抗匹配，并且具有减小的耗散。 线路驱动器包括包括第一和第二组电阻器的第一驱动器子电路。 为了驱动具有第一信号感测的输出节点，第一组电阻器被选择性地耦合到第一偏置电压端子，而第二组被选择性地耦合到第二偏置电压端子。 为了以第二信号检测来驱动第一输出节点，第一和第二组电阻器都选择性地耦合到第二偏置电压端子。 线路驱动器包括第二驱动器子电路。 第二驱动器分支电路包括相应地切换的第三组和第四组电阻器。