公开(公告)号：US4233615A

公开(公告)日：1980-11-11

申请号：US933045

申请日：1978-08-10

申请人： Toyoki Takemoto ,  Tadao Komeda ,  Haruyasu Yamada ,  Michihiro Inoue

发明人： Toyoki Takemoto ,  Tadao Komeda ,  Haruyasu Yamada ,  Michihiro Inoue

IPC分类号： H01L29/80 ,  H01L21/337 ,  H01L21/8222 ,  H01L21/8248 ,  H01L27/06 ,  H01L29/78 ,  H01L29/808

CPC分类号： H01L29/78 ,  H01L29/808

摘要： An IC device comprising a junction type field effect transistor of a back gate type and a bipolar device such as a bipolar transistor and a resistor made of impurity diffused region, wherein an extremely thin (in the order of 0.05-0.2 .mu.m) impurity doped surface region of a conductivity type same as that of a back gate region is formed at the surface of a surface channel region, and is separated from at least a drain region to sustain high breakdown voltage between gate region and the drain region; the impurity surface region serving to reduce noise and also enabling to achieve satisfactory characteristics of J-FET and also good ohmic characteristics of the resistor.

摘要翻译： 一种IC器件，包括背栅型的结型场效应晶体管和双极晶体管的双极器件和由杂质扩散区域制成的电阻器，其中极薄（约0.05-0.2μm）的杂质掺杂 在表面沟道区域的表面形成与背栅极区域相同的导电类型的表面区域，并且至少从漏极区域分离以维持栅极区域与漏极区域之间的高的击穿电压; 杂质表面区域用于降低噪声，并且还能够实现令人满意的J-FET特性和电阻器的良好欧姆特性。

公开(公告)号：US4826780A

公开(公告)日：1989-05-02

申请号：US124423

申请日：1987-11-23

申请人： Toyoki Takemoto ,  Tadao Komeda ,  Haruyasu Yamada ,  Tsutomu Fujita

发明人： Toyoki Takemoto ,  Tadao Komeda ,  Haruyasu Yamada ,  Tsutomu Fujita

IPC分类号： H01L21/74 ,  H01L21/761 ,  H01L21/8228 ,  H01L27/02 ,  H01L27/06 ,  H01L27/082 ,  H01L27/092 ,  H01L21/38

CPC分类号： H01L27/0244 ,  H01L21/74 ,  H01L21/761 ,  H01L21/82285 ,  H01L27/0623 ,  H01L27/0826 ,  H01L27/0922 ,  Y10S148/009 ,  Y10S148/151

摘要： In a semiconductor IC, a vertical pnp or npn transistor of a uniform characteristic and a high breakdown voltage is made by forming, for example, a p.sup.- -collector region (39) in an n-type epitaxial region, an n-well base region (41) formed in the p.sup.- -collector region (39) and a p-emitter region (42) formed in the n-well base region (41); and furthermore, for example as shown in FIG. 9, p.sup.- -regions (40) and (49) are formed simultaneously with the p.sup.- -collector region (39) and an n-region (53) is formed simultaneously with the n-well base region (41), thereby constituting IIL of superior characteristics and a high resistance device at the same time as forming of the vertical transistor without substantial increase of manufacturing steps; and in the similar way, by combining the p.sup.- -region and n-region formed in the above-mentioned simultaneous steps with other region formed simultaneously with the forming of the vertical transistor, high h.sub.FE transistor, high speed vertical npn transistor, cross-over devices, p-channel and/or n-channel MOS transistors can be formed within limited manufacturing steps.

摘要翻译： 在半导体IC中，通过在n型外延区域中形成例如p型集电极区域（39），形成具有均匀特性和高击穿电压的垂直pnp或npn晶体管，n阱基极 形成在p型集电极区域（39）中的区域（41）和形成在n阱基极区域（41）中的p型发射极区域（42）。 此外，例如如图1所示。 如图9所示，p-区域（40）和（49）与p-集电极区域（39）同时形成，并且与n-阱基区域（41）同时形成n区域（53），从而构成 IIL具有优越的特性和高电阻器件，同时形成垂直晶体管而不大幅度增加制造步骤; 并且以类似的方式，通过将在上述同步步骤中形成的p区域和n区域与形成垂直晶体管，高hFE晶体管，高速垂直npn晶体管， 可以在有限的制造步骤中形成器件，p沟道和/或n沟道MOS晶体管。

公开(公告)号：US4563807A

公开(公告)日：1986-01-14

申请号：US596592

申请日：1984-04-04

申请人： Hiroyuki Sakai ,  Toyoki Takemoto ,  Kenji Kawakita ,  Tsutomu Fujita ,  Atsuko Akiyama

发明人： Hiroyuki Sakai ,  Toyoki Takemoto ,  Kenji Kawakita ,  Tsutomu Fujita ,  Atsuko Akiyama

IPC分类号： H01L21/20 ,  H01L21/203 ,  H01L21/285 ,  H01L21/331 ,  H01L29/73 ,  H01L29/732 ,  H01L21/225

CPC分类号： H01L29/7325 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02631 ,  H01L21/28525 ,  Y10S148/123 ,  Y10S148/124 ,  Y10S148/169

摘要： Semiconductor device, such as bipolar transistor, is made by molecular beam epitaxy, wherein a emitter layer (27) and overriding contact regions (28) of polycrystalline silicon are grown continuously on a silicon substrate (23+26) without breaking high vacuum, thus eliminating the adverse interface of natural oxide film under the polycrystalline silicon layer (28) and the adverse donor-acceptor compensation while attaining a well controlled h.sub.FE and enabling a shallow emitter junction.

摘要翻译： 诸如双极晶体管的半导体器件通过分子束外延制造，其中发射极层（27）和多晶硅的覆盖接触区域（28）在硅衬底（23 + 26）上连续生长而不破坏高真空，因此 消除多晶硅层（28）下的自然氧化膜的不利界面和不利的供体 - 受体补偿，同时实现良好控制的hFE并实现浅发射极结。

公开(公告)号：US4484211A

公开(公告)日：1984-11-20

申请号：US542555

申请日：1983-10-17

申请人： Toyoki Takemoto ,  Tsutomu Fujita ,  Hiroyuki Sakai ,  Haruyasu Yamada

发明人： Toyoki Takemoto ,  Tsutomu Fujita ,  Hiroyuki Sakai ,  Haruyasu Yamada

IPC分类号： H01L29/06 ,  H01L29/732 ,  H01L27/04 ,  H01L29/04 ,  H01L29/72

CPC分类号： H01L29/7325 ,  H01L29/0649

摘要： A semiconductor integrated circuit device in which the side surfaces of an emitter of an oxide isolated bipolar transistor are surrounded with insulating compounds or regions so that the capacitance between the emitter and base is lowered and a base is formed by the self-alignment so that the influence of an active base between an external base and the emitter can be made negligible. Thus the base resistance and parasitic capacitance are lowered.

摘要翻译： 一种半导体集成电路器件，其中氧化物隔离双极晶体管的发射极的侧表面被绝缘化合物或区域包围，使得发射极和基极之间的电容降低，并且通过自对准形成基极， 活性碱在外部碱基和发光体之间的影响可以忽略不计。 因此，基极电阻和寄生电容降低。

公开(公告)号：US4417233A

公开(公告)日：1983-11-22

申请号：US123646

申请日：1980-02-22

申请人： Michihiro Inoue ,  Toyoki Takemoto ,  Haruyasu Yamada

发明人： Michihiro Inoue ,  Toyoki Takemoto ,  Haruyasu Yamada

IPC分类号： H03M1/00 ,  H03K13/03

CPC分类号： H03M1/361

摘要： A parallel type A/D converter capable of operating at an extremely high speed with a high degree of accuracy and with low power consumption. A plurality of comparators each having a reference voltage corresponding to an assigned quantizing level are disposed in parallel with each other and divided into a plurality of comparator blocks or groups. A plurality of sub-comparators are provided so that prior to the comparison of the input signal by the comparators, the input signal is first compared with the reference voltages of the sub-comparators and in response to the output from the sub-comparator having the reference voltage comparable or corresponding to the incoming input signal, only the comparators in the comparator block or group associated with said sub-comparator are energized or enabled while the remaining comparators are kept de-energized or disabled, whereby a minimum power consumption may be attained.

摘要翻译： 一种并联型A / D转换器，能够以极高的精度和低功耗运行。 每个具有与分配的量化电平相对应的参考电压的多个比较器彼此并联设置并分成多个比较器块或组。 提供多个子比较器，使得在比较器比较输入信号之前，首先将输入信号与子比较器的参考电压进行比较，并且响应于具有该比较器的子比较器的输出 与输入输入信号相当或对应的参考电压，只有与所述子比较器相关联的比较器块或组中的比较器通电或使能，而剩余的比较器保持断电或禁用，从而可以获得最小的功率消耗 。

公开(公告)号：US4201106A

公开(公告)日：1980-05-06

申请号：US799316

申请日：1977-05-23

申请人： Takeji Kimura ,  Toyoki Takemoto ,  Michihiro Inoue ,  Masaharu Sato

发明人： Takeji Kimura ,  Toyoki Takemoto ,  Michihiro Inoue ,  Masaharu Sato

IPC分类号： G10H1/057 ,  G10H1/18 ,  G10H7/00 ,  G10H3/00 ,  G10H1/02

CPC分类号： G10H1/182 ,  G10H1/057 ,  G10H7/00 ,  Y10S84/07

摘要： The present invention is an electronic musical instrument the type in which information of the actuation of keys is detected by scanning the keys of a keyboard. The electronic musical instrument includes keys selectively actuable for producing sounds which correspond to respective musical scale notes, circuitry for sequentially scanning these keys for detection of the information of the actuation of these keys, and a memory circuit corresponding to each of the keys so that the information of the actuation of the keys is stored in the memory circuits.

摘要翻译： 本发明是一种电子乐器，其中通过扫描键盘的键来检测键的致动信息。 电子乐器包括可选择地致动的用于产生对应于各个音阶音符的声音的键，用于顺序地扫描这些键的电路，用于检测这些键的致动信息，以及对应于每个键的存储电路， 钥匙的致动信息被存储在存储器电路中。