公开(公告)号：US20110297975A1

公开(公告)日：2011-12-08

申请号：US13212208

申请日：2011-08-18

Applicant: Wen-Yung Yeh ,  Chia-Hsin Chao ,  Yu-Hung Chuang ,  Chia-Ling Li ,  Chun-Feng Lai ,  Hsi-Hsuan Yen ,  Sheng-Chieh Tai ,  Kuang-Yu Tai ,  Tse-Peng Chen

Inventor： Wen-Yung Yeh ,  Chia-Hsin Chao ,  Yu-Hung Chuang ,  Chia-Ling Li ,  Chun-Feng Lai ,  Hsi-Hsuan Yen ,  Sheng-Chieh Tai ,  Kuang-Yu Tai ,  Tse-Peng Chen

IPC: H01L27/15

CPC classification number: H04N9/315 ,  G03B21/005 ,  H01L27/156 ,  H01L33/504 ,  H01L33/60 ,  H01L2933/0083

Abstract: A light-emitting unit array includes a plurality of light-emitting units arranged and integrated monolithically in an array, and each of the light-emitting units includes a first doped type layer, a second doped type layer, a light-emission layer, and a photonic crystal structure. The light emission layer is disposed between the first doped type layer and the second doped type layer, wherein the second doped type layer has a surface facing away from the light emission layer. The photonic crystal structure is disposed on the surface of the second doped type layer.

Abstract translation: 发光单元阵列包括以阵列的方式排列并集成的多个发光单元，并且每个发光单元包括第一掺杂型层，第二掺杂型层，发光层和 光子晶体结构。 发光层设置在第一掺杂型层和第二掺杂型层之间，其中第二掺杂型层具有背离发光层的表面。 光子晶体结构设置在第二掺杂型层的表面上。

公开(公告)号：US20090079479A1

公开(公告)日：2009-03-26

申请号：US11861260

申请日：2007-09-25

Applicant: Tse-Peng Chen

Inventor： Tse-Peng Chen

IPC: H03L7/08

CPC classification number: H03L7/095

Abstract: An adjustable digital lock detector for a phase-locked loop (PLL) has a variable counter for outputting an output signal corresponding to a first clock signal, a target count number signal, and a count number offset signal, a latch for sampling the output signal of the variable counter and outputting a latch output signal according to a result of sampling the output signal, a lead/lag detector for receiving the latch output signal and outputting the count number offset signal according to a predetermined state of the latch output signal, and an arbiter for receiving the latch output signal and outputting an arbiter output signal according to the latch output signal and a second clock signal.

Abstract translation: 用于锁相环（PLL）的可调数字锁定检测器具有可变计数器，用于输出对应于第一时钟信号，目标计数数信号和计数数偏移信号的输出信号，用于对输出信号进行采样的锁存器 根据所述输出信号的采样结果输出锁存输出信号;引导/延迟检测器，用于接收所述锁存输出信号，并根据所述锁存输出信号的预定状态输出所述计数数字偏移信号;以及 用于接收锁存器输出信号并根据锁存输出信号和第二时钟信号输出仲裁器输出信号的仲裁器。

公开(公告)号：US20090055677A1

公开(公告)日：2009-02-26

申请号：US11892238

申请日：2007-08-21

Applicant: Tse-Peng Chen

Inventor： Tse-Peng Chen

IPC: G06F13/38 ,  G06F1/04

CPC classification number: G06F1/04 ,  G06F13/4059

Abstract: The invention provides an asynchronous first in first out (FIFO) interface and operation method wherein a read-out clock and a write-in clock of the asynchronous FIFO interface is asynchronous. The asynchronous FIFO interface comprises a FIFO buffer, a clock controller and a variable integer divider. The FIFO buffer inputs at least one data with the write-in clock, and outputs the at least one data with the read-out clock. The clock controller outputs a clock control signal according to a number of data stored in the FIFO buffer. The variable integer divider divides a first signal to generate the read-out clock or the write-in clock by an integer divisor controlled by the clock control signal in order to adjust the number of data stored in the FIFO buffer.

Abstract translation: 本发明提供了异步先进先出（FIFO）接口和操作方法，其中异步FIFO接口的读出时钟和写入时钟是异步的。 异步FIFO接口包括FIFO缓冲器，时钟控制器和可变整数分频器。 FIFO缓冲器至少输入一个具有写入时钟的数据，并输出至少一个具有读出时钟的数据。 时钟控制器根据存储在FIFO缓冲器中的数据数量输出时钟控制信号。 可变整数分频器分割第一信号以通过由时钟控制信号控制的整数除数来产生读出时钟或写入时钟，以便调整存储在FIFO缓冲器中的数据的数量。