公开(公告)号：US20220238542A1

公开(公告)日：2022-07-28

申请号：US17177211

申请日：2021-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Xiaojuan Gao ,  CHI REN

IPC: H01L27/11531 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/788 ,  H01L29/66

Abstract: A flash includes a substrate. Two gate structures are disposed on the substrate. Each of the gate structures includes a floating gate and a control gate. The control gate is disposed on the floating gate. An erase gate is disposed between the gate structures. Two word lines are respectively disposed at a side of each of the gate structures. A top surface of each of the word lines includes a first concave surface and a sharp angle. The sharp angle is closed to a sidewall of the word line which the sharp angle resided. The sidewall is away from each of the gate structures. The shape angle connects to the first concave surface.

公开(公告)号：US20150014761A1

公开(公告)日：2015-01-15

申请号：US13939186

申请日：2013-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yuan Hsu ,  ZHEN CHEN ,  CHI REN ,  Ching-Long Tsai ,  Wei Cheng ,  PING LIU

IPC: H01L21/28 ,  H01L29/423

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method for manufacturing a semiconductor device includes the following steps. At first, two gate stack layers are formed on a semiconductor substrate, wherein each of the gate stack layers includes a top surface and two side surfaces. A conductive material layer is deposited to conformally cover the top surface and the two side surfaces of each of the gate stack layers. Then, a cap layer is deposited to conformally cover the conductive material layer. Finally, the cap layer and the conductive material layer above the top surface of each of the gate stack layers are removed to leave the cap layer adjacent to the two side surfaces of each of the gate stack layers and covering a portion of the conductive material layer.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 首先，在半导体衬底上形成两个栅极堆叠层，其中每个栅极堆叠层包括顶表面和两个侧表面。 沉积导电材料层以共形地覆盖每个栅极堆叠层的顶表面和两个侧表面。 然后，沉积覆盖层以覆盖导电材料层。 最后，去除盖层和每个栅极堆叠层的顶表面上方的导电材料层，以使覆盖层与每个栅极叠层层的两个侧表面相邻并且覆盖导电材料层的一部分 。

公开(公告)号：US20240074174A1

公开(公告)日：2024-02-29

申请号：US17952322

申请日：2022-09-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  CHI REN

IPC: H01L27/11521 ,  H01L27/11519 ,  H01L27/11539

CPC classification number: H01L27/11521 ,  H01L27/11519 ,  H01L27/11539

Abstract: A memory device includes a semiconductor substrate, isolation structures, an erase gate, and floating gates. The isolation structures are disposed in the semiconductor substrate. Active regions separated from one another are defined in the semiconductor substrate by the isolation structures, and each of the active regions is elongated in a first direction. The erase gate is disposed on the semiconductor substrate and elongated in a second direction. The erase gate is disposed on the active regions and the isolation structures, and the erase gate is partly disposed in a recess within each of the isolation structures. The floating gates are disposed on the semiconductor substrate. The floating gates are arranged in the second direction and separated from one another, and each of the floating gates is partly disposed under the erase gate in a vertical direction.

公开(公告)号：US20230029468A1

公开(公告)日：2023-02-02

申请号：US17510371

申请日：2021-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  ZHIGUO LI ,  Xiaojuan Gao ,  CHI REN

IPC: H01L29/423 ,  H01L29/788 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor memory device includes a substrate; a source diffusion region in the substrate; a pair of floating gates disposed on opposite of the source diffusion region; a first dielectric cap layer disposed directly on each of the floating gates; an erase gate disposed on the source diffusion region and partially overlapping an upper inner corner of each of the floating gates; a second dielectric cap layer disposed on the erase gate and the first dielectric cap layer; a select gate disposed on a sidewall of the first dielectric cap layer; and a drain diffusion region disposed in the substrate and adjacent to the select gate.

公开(公告)号：US20220352190A1

公开(公告)日：2022-11-03

申请号：US17863367

申请日：2022-07-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Xiaojuan Gao ,  CHI REN

IPC: H01L27/11531 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11529 ,  H01L27/11524

Abstract: A flash includes a substrate. Two gate structures are disposed on the substrate. Each of the gate structures includes a floating gate and a control gate. The control gate is disposed on the floating gate. An erase gate is disposed between the gate structures. Two word lines are respectively disposed at a side of each of the gate structures. A top surface of each of the word lines includes a first concave surface and a sharp angle. The sharp angle is closed to a sidewall of the word line which the sharp angle resided. The sidewall is away from each of the gate structures. The sharp angle connects to the first concave surface.

公开(公告)号：US20220262749A1

公开(公告)日：2022-08-18

申请号：US17160400

申请日：2021-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Aaron Chen ,  CHI REN ,  YI HSIN LIU

IPC: H01L23/00 ,  H01L23/522

Abstract: An integrated circuit structure includes a substrate with a circuit region thereon and a copper interconnect structure disposed on the substrate. The copper interconnect structure includes an uppermost copper layer covered by a dielectric layer. An aluminum pad layer is provided on the dielectric layer. A metal layer is provided on the circuit region and is located between the uppermost copper layer and the aluminum pad layer.

公开(公告)号：US20150115346A1

公开(公告)日：2015-04-30

申请号：US14062905

申请日：2013-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yuan Hsu ,  ZHIGUO LI ,  CHI REN

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/11521 ,  H01L29/42324 ,  H01L29/66825

Abstract: A semiconductor memory device includes a substrate, shallow trench isolations protruding from the substrate, a floating gate formed conformally on the surface of the recess between each shallow trench isolation, a tunnel layer formed between each floating gate and the substrate, a dielectric layer formed conformally on the floating gates, and a control gate formed on the dielectric layer.

Abstract translation: 半导体存储器件包括衬底，从衬底突出的浅沟槽隔离物，在每个浅沟槽隔离件之间的凹槽表面上共形形成的浮栅，在每个浮置栅极和衬底之间形成的隧道层，保形地形成的电介质层 在浮置栅极上，以及形成在电介质层上的控制栅极。

公开(公告)号：US20140377945A1

公开(公告)日：2014-12-25

申请号：US13923374

申请日：2013-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yuan Hsu ,  ZHAOBING LI ,  CHI REN ,  Ching-Long Tsai ,  Wei Cheng

IPC: H01L21/28

CPC classification number: H01L21/28273 ,  H01L21/3212

Abstract: A floating gate forming process includes the following steps. A substrate containing active areas isolated from each other by isolation structures protruding from the substrate is provided. A first conductive material is formed to conformally cover the active areas and the isolation structure. An etch back process is performed on the first conductive material to respectively form floating gates separated from each other in the active areas.

Abstract translation: 浮栅形成工艺包括以下步骤。 提供了包含通过从衬底突出的隔离结构彼此隔离的有源区的衬底。 第一导电材料形成为保形地覆盖有源区域和隔离结构。 对第一导电材料进行回蚀处理，以分别形成在有源区域中彼此分离的浮动栅极。