公开(公告)号：US20200135274A1

公开(公告)日：2020-04-30

申请号：US16173406

申请日：2018-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： LIANG YI ,  ZHAOBING LI ,  CHI REN

IPC: G11C16/04 ,  H01L27/11517 ,  G11C13/00 ,  H01L45/00

Abstract: A structure of nonvolatile memory device includes a substrate, having a logic device region and a memory cell region. A first gate structure for a low-voltage transistor is disposed over the substrate in the logic device region, wherein the first gate structure comprises a single-layer polysilicon. A second gate structure for a memory cell is disposed over the substrate in the memory cell region. The second gate structure includes a gate insulating layer on the substrate. A floating gate layer is disposed on the gate insulating layer, wherein the floating gate layer comprises a first polysilicon layer and a second polysilicon layer as a stacked structure. A memory dielectric layer is disposed on the floating gate layer. A control gate layer is disposed on the memory dielectric layer, wherein the control gate layer and the single-layer polysilicon are originated from a preliminary polysilicon layer in same.

公开(公告)号：US20140183614A1

公开(公告)日：2014-07-03

申请号：US13733147

申请日：2013-01-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHAOBING LI ,  Cheng-Yuan Hsu ,  CHI REN

IPC: H01L29/788

CPC classification number: H01L29/42324 ,  H01L21/76224 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7881

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, at least a first gate, a shallow trench isolation (STI) and a third gate. The first gate is disposed on the semiconductor substrate, and the first gate partially overlaps the third gate and the shallow trench isolation. Furthermore, the third gate is disposed in a shallow trench isolation, and the third gate includes at least a protrusion.

Abstract translation: 提供半导体器件。 半导体器件包括半导体衬底，至少第一栅极，浅沟槽隔离（STI）和第三栅极。 第一栅极设置在半导体衬底上，第一栅极部分地与第三栅极重叠并且浅沟槽隔离。 此外，第三栅极设置在浅沟槽隔离中，并且第三栅极至少包括突起。

公开(公告)号：US20140377945A1

公开(公告)日：2014-12-25

申请号：US13923374

申请日：2013-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yuan Hsu ,  ZHAOBING LI ,  CHI REN ,  Ching-Long Tsai ,  Wei Cheng

IPC: H01L21/28

CPC classification number: H01L21/28273 ,  H01L21/3212

Abstract: A floating gate forming process includes the following steps. A substrate containing active areas isolated from each other by isolation structures protruding from the substrate is provided. A first conductive material is formed to conformally cover the active areas and the isolation structure. An etch back process is performed on the first conductive material to respectively form floating gates separated from each other in the active areas.

Abstract translation: 浮栅形成工艺包括以下步骤。 提供了包含通过从衬底突出的隔离结构彼此隔离的有源区的衬底。 第一导电材料形成为保形地覆盖有源区域和隔离结构。 对第一导电材料进行回蚀处理，以分别形成在有源区域中彼此分离的浮动栅极。