公开(公告)号：US12283557B2

公开(公告)日：2025-04-22

申请号：US18398204

申请日：2023-12-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Aaron Chen ,  Chi Ren ,  Yi Hsin Liu

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

Abstract: An integrated circuit structure includes an aluminum pad layer on a dielectric stack, a passivation layer covering the aluminum pad layer, and an aluminum shield layer including aluminum routing patterns disposed directly above an embedded memory area and embedded in the dielectric stack. The aluminum shield layer is electrically connected to the uppermost copper layer through a plurality of tungsten vias. The plurality of tungsten vias is embedded in the dielectric stack.

公开(公告)号：US20240260263A1

公开(公告)日：2024-08-01

申请号：US18629926

申请日：2024-04-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Aaron Chen ,  Chi Ren ,  Chao-Sheng Hsieh

IPC: H10B41/30 ,  H10B41/60

CPC classification number: H10B41/30 ,  H10B41/60

Abstract: An electrically erasable programmable read only memory (EEPROM) cell includes a first gate, a second gate and an erasing gate. The first gate and the second gate are disposed on a substrate, wherein the first gate includes a first floating gate and a first control gate stacked from bottom to top, and the second gate includes a second floating gate and a second control gate stacked from bottom to top. The erasing gate is sandwiched by the first gate and the second gate, wherein a side part of the first floating gate and a side part of the second floating gate right below the erasing gate both have multiple tips. The present invention also provides a method of forming the electrically erasable programmable read only memory (EEPROM) cell.

公开(公告)号：US20230128356A1

公开(公告)日：2023-04-27

申请号：US17527182

申请日：2021-11-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Aaron Chen ,  CHI REN ,  Chao-Sheng Hsieh

IPC: H01L27/11521 ,  H01L27/11558

Abstract: An electrically erasable programmable read only memory (EEPROM) cell includes a first gate, a second gate and an erasing gate. The first gate and the second gate are disposed on a substrate, wherein the first gate includes a first floating gate and a first control gate stacked from bottom to top, and the second gate includes a second floating gate and a second control gate stacked from bottom to top. The erasing gate is sandwiched by the first gate and the second gate, wherein a side part of the first floating gate and a side part of the second floating gate right below the erasing gate both have multiple tips. The present invention also provides a method of forming said electrically erasable programmable read only memory (EEPROM) cell.

公开(公告)号：US20160163722A1

公开(公告)日：2016-06-09

申请号：US14596227

申请日：2015-01-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan-Hsiang Chang ,  Aaron Chen ,  JIANJUN YANG ,  Chih-Chien Chang

IPC: H01L27/115 ,  H01L29/66 ,  H01L21/321 ,  H01L21/28 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/788 ,  H01L29/423

CPC classification number: H01L27/11521 ,  H01L27/11534 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788

Abstract: A non-volatile memory cell includes a substrate, an erase gate disposed on the substrate and having a top plane, two floating gates disposed respectively at both sides of the erase gate, two control gates disposed respectively on two floating gates, and two select gates disposed respectively at outer sides of the two floating gates, where the two select gates have tilted top planes which are symmetric to each other.

Abstract translation: 非易失性存储单元包括衬底，设置在衬底上的擦除栅极，具有顶面，分别设置在擦除栅极两侧的两个浮置栅极，分别设置在两个浮置栅极上的两个控制栅极和两个选择栅极 分别设置在两个浮动栅极的外侧，其中两个选择栅极具有彼此对称的倾斜顶部平面。

公开(公告)号：US20240128214A1

公开(公告)日：2024-04-18

申请号：US18398204

申请日：2023-12-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Aaron Chen ,  Chi Ren ,  Yi Hsin Liu

IPC: H01L23/00 ,  H01L23/522

CPC classification number: H01L24/05 ,  H01L23/5226 ,  H01L24/03 ,  H01L23/53228 ,  H01L2224/0391 ,  H01L2924/1438 ,  H01L2924/14511

Abstract: An integrated circuit structure includes an aluminum pad layer on a dielectric stack, a passivation layer covering the aluminum pad layer, and an aluminum shield layer including aluminum routing patterns disposed directly above an embedded memory area and embedded in the dielectric stack. The aluminum shield layer is electrically connected to the uppermost copper layer through a plurality of tungsten vias. The plurality of tungsten vias is embedded in the dielectric stack.

公开(公告)号：US20170301683A1

公开(公告)日：2017-10-19

申请号：US15132574

申请日：2016-04-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Aaron Chen ,  Chi Ren

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788 ,  H01L29/06

CPC classification number: H01L27/11546 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

Abstract: A semiconductor device with split gate flash memory cell structure includes a substrate having a first area and a second area, at least a first cell formed in the first area and at least a second cell formed in the second area. The first cell includes a first dielectric layer formed on the substrate, a floating gate (FG), a word line and an erase gate (EG) formed on the first dielectric layer, an interlayer dielectric (ILD) layer, an inter-gate dielectric layer and a control gate (CG). The FG is positioned between the word line and the EG, and the ILD layer is formed on the word line and the EG, wherein the ILD layer has a trench exposing the FG. The inter-gate dielectric layer is formed in the trench as a liner, and the CG formed in the trench is surrounded by the inter-gate dielectric layer.

公开(公告)号：US09837425B2

公开(公告)日：2017-12-05

申请号：US15132574

申请日：2016-04-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Aaron Chen ,  Chi Ren

IPC: H01L29/66 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/11546 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

Abstract: A semiconductor device with split gate flash memory cell structure includes a substrate having a first area and a second area, at least a first cell formed in the first area and at least a second cell formed in the second area. The first cell includes a first dielectric layer formed on the substrate, a floating gate (FG), a word line and an erase gate (EG) formed on the first dielectric layer, an interlayer dielectric (ILD) layer, an inter-gate dielectric layer and a control gate (CG). The FG is positioned between the word line and the EG, and the ILD layer is formed on the word line and the EG, wherein the ILD layer has a trench exposing the FG. The inter-gate dielectric layer is formed in the trench as a liner, and the CG formed in the trench is surrounded by the inter-gate dielectric layer.

公开(公告)号：US20170141200A1

公开(公告)日：2017-05-18

申请号：US14944224

申请日：2015-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan-Hsiang Chang ,  Shen-De Wang ,  Chih-Chien Chang ,  JIANJUN YANG ,  Aaron Chen

IPC: H01L29/423 ,  H01L21/28 ,  H01L21/265 ,  H01L21/321 ,  H01L27/115 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/788 ,  H01L29/51 ,  H01L29/66 ,  H01L21/223

CPC classification number: H01L29/42328 ,  H01L21/26586 ,  H01L21/28273 ,  H01L21/28562 ,  H01L21/31111 ,  H01L21/321 ,  H01L21/32133 ,  H01L27/11521 ,  H01L28/00 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/788

Abstract: A flash cell includes a gate and an erase gate. The gate is disposed on a substrate, wherein the gate includes a control gate on the substrate and a floating gate having a tip between the substrate and the control gate. The erase gate is disposed beside the gate, wherein the tip points toward the erase gate. The present invention also provides a flash cell forming process including the following steps. A gate is formed on a substrate, wherein the gate includes a floating gate on the substrate. An implantation process is performed on a side part of the floating gate, thereby forming a first doped region in the side part. At least a part of the first doped region is oxidized, thereby forming a floating gate having a tip.

公开(公告)号：US11901318B2

公开(公告)日：2024-02-13

申请号：US17160400

申请日：2021-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Aaron Chen ,  Chi Ren ,  Yi Hsin Liu

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L24/05 ,  H01L23/5226 ,  H01L24/03 ,  H01L23/53228 ,  H01L23/53257 ,  H01L2224/024 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0391 ,  H01L2224/05546 ,  H01L2224/05624 ,  H01L2924/1438 ,  H01L2924/14511

Abstract: An integrated circuit structure includes a substrate with a circuit region thereon and a copper interconnect structure disposed on the substrate. The copper interconnect structure includes an uppermost copper layer covered by a dielectric layer. An aluminum pad layer is provided on the dielectric layer. A metal layer is provided on the circuit region and is located between the uppermost copper layer and the aluminum pad layer.

公开(公告)号：US20220262749A1

公开(公告)日：2022-08-18

申请号：US17160400

申请日：2021-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Aaron Chen ,  CHI REN ,  YI HSIN LIU

IPC: H01L23/00 ,  H01L23/522

Abstract: An integrated circuit structure includes a substrate with a circuit region thereon and a copper interconnect structure disposed on the substrate. The copper interconnect structure includes an uppermost copper layer covered by a dielectric layer. An aluminum pad layer is provided on the dielectric layer. A metal layer is provided on the circuit region and is located between the uppermost copper layer and the aluminum pad layer.