公开(公告)号：US20240147683A1

公开(公告)日：2024-05-02

申请号：US17994381

申请日：2022-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Wei Yeh ,  Chang-Hung Chen

IPC: H01L27/11

CPC classification number: H01L27/1104

Abstract: The invention provides a layout pattern of static random access memory, which comprises a plurality of fin structures on a substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate. The transistors include a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2) and a second pull-down transistor (PD2), a first access transistor (PG1), a second access transistor (PG2), a first read port transistor (RPD) and a second read port transistor (RPG). The gate structure of the first read port transistor (RPD) is connected to the gate structure of the first pull-down transistor (PD1), wherein a drain of the first pull-down transistor (PD1) is connected to a first voltage source Vss1, and a drain of the first read port transistor (RPD) is connected to a second voltage source Vss2.

公开(公告)号：US20230018513A1

公开(公告)日：2023-01-19

申请号：US17952327

申请日：2022-09-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Shu-Ru Wang ,  Yu-Tse Kuo ,  Chang-Hung Chen ,  Yi-Ting Wu ,  Shu-Wei Yeh ,  Ya-Lan Chiou ,  Chun-Hsien Huang

IPC: H01L27/22 ,  H01L43/02

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region and a second cell region and a diffusion region on the substrate extending through the first cell region and the second cell region. Preferably, the diffusion region includes a first H-shape and a second H-shape according to a top view.

公开(公告)号：US10607981B2

公开(公告)日：2020-03-31

申请号：US16101528

申请日：2018-08-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Wei Yeh ,  Chang-Hung Chen

IPC: H01L27/02 ,  G11C11/412 ,  H01L27/11 ,  G11C11/417 ,  G11C8/16

Abstract: The present invention provides a layout pattern of a static random access memory (SRAM), comprising at least one substrate, two SRAM units on the substrate, respectively located in a first region and a second region which is adjacent to the first region. Each of the SRAM units includes a first inverter coupled to a second inverter and configured to form a latching circuit, the first inverter includes a first pull-up transistor (PU1) and a first pull-down transistor (PD1), the second inverter includes a second pull-up transistor (PU2) and a second pull-down transistor (PD2). A dummy layer crossing the first a region and the second region, and between the PD1 in the first region and the PD1 in the second region, and a contact structure on the dummy layer, electrically connected to a voltage source Vss.

公开(公告)号：US10529723B2

公开(公告)日：2020-01-07

申请号：US15186548

申请日：2016-06-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Wei Yeh ,  Tsung-Hsun Wu ,  Chih-Ming Su ,  Yu-Tse Kuo

IPC: H01L27/11 ,  H01L27/02

Abstract: A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device and a second pass gate device disposed on a substrate. A plurality of fin structures are disposed on the substrate, and the fin structures include at least one first fin structure and at least one second fin structure. A J-shaped gate structure is disposed on the substrate, including a long part, a short part and a bridge part. At least one first extending contact structure crosses over the at least one first fin structure and the at least one second fin structure, wherein the at least one first extending contact structure does not overlap with the bridge part of the J-shaped gate structure.

公开(公告)号：US20170323894A1

公开(公告)日：2017-11-09

申请号：US15186548

申请日：2016-06-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Wei Yeh ,  Tsung-Hsun Wu ,  Chih-Ming Su ,  Yu-Tse Kuo

IPC: H01L27/11 ,  H01L29/10 ,  H01L27/088 ,  H01L27/02 ,  H01L23/532 ,  H01L29/423 ,  H01L23/528

CPC classification number: H01L27/1104 ,  G11C8/14 ,  G11C11/412 ,  G11C11/418 ,  G11C14/0054 ,  H01L27/0207 ,  H01L27/0924

Abstract: A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device and a second pass gate device disposed on a substrate. A plurality of fin structures are disposed on the substrate, and the fin structures include at least one first fin structure and at least one second fin structure. A J-shaped gate structure is disposed on the substrate, including a long part, a short part and a bridge part. At least one first extending contact structure crosses over the at least one first fin structure and the at least one second fin structure, wherein the at least one first extending contact structure does not overlap with the bridge part of the J-shaped gate structure.