公开(公告)号：US10600732B1

公开(公告)日：2020-03-24

申请号：US16122807

申请日：2018-09-05

Applicant: United Microelectronics Corp.

Inventor： Min-Shiang Hsu ,  Yu-Han Tsai ,  Yi-Hsiu Chen ,  Chih-Sheng Chang

IPC: H01L29/40 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: A structure of semiconductor device includes a substrate. An interconnection layer is formed on the substrate including a first inter-layer dielectric (ILD) layer over the substrate. A lower wiring structure is formed in the ILD layer. A hard mask layer is disposed on the first ILD layer. The hard mask layer has a first opening and a second opening being adjacent to expose the lower wiring structure. A second ILD layer is disposed on the hard mask layer. The second ILD layer has a via opening aligned to the first opening of the mask layer and a trench pattern connecting with the via opening. The second ILD layer has a protruding portion to fill the second opening of the mask layer. A metal line layer fills the via opening and the trench pattern in the second ILD layer and the first opening of the hard mask layer.

公开(公告)号：US12154852B2

公开(公告)日：2024-11-26

申请号：US17670520

申请日：2022-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Min-Shiang Hsu ,  Yu-Han Tsai ,  Chih-Sheng Chang

IPC: H01L23/522 ,  H01L21/768

Abstract: An interconnection structure includes a first interconnection level, a second interconnection level, a third interconnection level, and a super via structure. The second interconnection level is disposed on the first interconnection level, and the third interconnection level is disposed on the second interconnection level. The second interconnection level includes a second conductive layer and a block layer disposed in a dielectric layer. A bottom surface of the block layer is lower than a top surface of the second conductive layer in a vertical direction. The block layer is disposed between a first conductive layer of the first interconnection level and a third conductive layer of the third interconnection level in the vertical direction. The super via structure penetrates through the block layer and the second interconnection level in the vertical direction and electrically connects the first conductive layer and the third conductive layer.

公开(公告)号：US12057346B2

公开(公告)日：2024-08-06

申请号：US18243096

申请日：2023-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Chih Chang ,  Yuan-Fu Ko ,  Chih-Sheng Chang

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/02164 ,  H01L21/0217 ,  H01L23/528 ,  H01L23/53295

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the first metal interconnection; forming a second IMD layer on the spacer and the first metal interconnection; and forming a second metal interconnection in the second IMD layer and on the spacer and the first metal interconnection.

公开(公告)号：US11784214B2

公开(公告)日：2023-10-10

申请号：US17899807

申请日：2022-08-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bo-Wei Huang ,  Chun-Wei Kang ,  Ho-Yu Lai ,  Chih-Sheng Chang

IPC: H01L23/64 ,  H01L49/02

CPC classification number: H01L28/84 ,  H01L23/642 ,  H01L28/40

Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor is provided. The MIM capacitor includes a substrate, a first metal layer, a deposition structure, a dielectric layer and a second metal layer. The first metal layer is disposed on the substate and has a planarized surface. The deposition structure is disposed on the first metal layer, and at least a portion of the deposition structure extends into the planarized surface, wherein the first metal layer and the deposition structure have the same material. The dielectric layer is disposed on the deposition structure. The second metal layer is disposed on the dielectric layer.

公开(公告)号：US20230050928A1

公开(公告)日：2023-02-16

申请号：US17472577

申请日：2021-09-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Che Huang ,  Ching-Chih Chang ,  Yuan-Fu Ko ,  Chih-Sheng Chang

IPC: H01L23/528 ,  H01L23/522

Abstract: A semiconductor device includes a first metal interconnection disposed on a substrate, a second metal interconnection disposed on the first metal interconnection, a first contact via disposed between the first metal interconnection and the second metal interconnection, a first serpent metal line connecting to a first end of the first metal interconnection, and a second serpent metal line connecting to a second end of the first metal interconnection. Preferably, the first serpent metal line, the second serpent metal line, and the first metal interconnection are on a same level.

公开(公告)号：US20210159170A1

公开(公告)日：2021-05-27

申请号：US16709934

申请日：2019-12-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Min-Shiang Hsu ,  Yu-Han Tsai ,  Chih-Sheng Chang

IPC: H01L23/522 ,  H01L21/768

Abstract: An interconnection structure includes a first interlayer dielectric layer, a first conductive line, a protection layer, a second interlayer dielectric layer, and a connection plug. The first conductive line is partially disposed in the first interlayer dielectric layer. The protection layer is disposed on the first conductive line and the first interlayer dielectric layer. The protection layer covers a top surface and a sidewall of the first conductive line. The protection layer includes a recess disposed corresponding to the first conductive line in a vertical direction. The second interlayer dielectric layer is disposed on the protection layer. The connection plug penetrates at least a part of the second interlayer dielectric layer and the protection layer for being connected with the first conductive line.

公开(公告)号：US10978391B2

公开(公告)日：2021-04-13

申请号：US15730744

申请日：2017-10-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Yi Weng ,  Shih-Che Huang ,  Ching-Li Yang ,  Chih-Sheng Chang

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L23/498

Abstract: A connection structure of a semiconductor device is provided in the present invention. The connection structure includes an interlayer dielectric, a top metal structure, and a passivation layer. The interlayer dielectric is disposed on a substrate. The top metal structure is disposed on the interlayer dielectric. The top metal structure includes a bottom portion and a top portion disposed on the bottom portion. The bottom portion includes a first sidewall, and the top portion includes a second sidewall. A slope of the first sidewall is larger than a slope of the second sidewall. The passivation layer is conformally disposed on the second sidewall, the first sidewall, and a top surface of the interlayer dielectric.

公开(公告)号：US10784153B2

公开(公告)日：2020-09-22

申请号：US16134902

申请日：2018-09-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-How Chou ,  Tzu-Hao Fu ,  Tsung-Yin Hsieh ,  Chih-Sheng Chang ,  Shih-Chun Tsai ,  Kun-Chen Ho ,  Yang-Chou Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method for fabricating metal interconnect structure includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer on a substrate; forming a cap layer on the first metal interconnection; forming a second IMD layer on the cap layer; performing a first etching process to remove part of the second IMD layer for forming an opening; performing a plasma treatment process; and performing a second etching process to remove polymers from bottom of the opening.

公开(公告)号：US20200066657A1

公开(公告)日：2020-02-27

申请号：US16135997

申请日：2018-09-19

Applicant: United Microelectronics Corp.

Inventor： Shih-Che Huang ,  Shih-Hsien Chen ,  Ching-Li Yang ,  Chih-Sheng Chang

IPC: H01L23/58 ,  H01L23/10 ,  H01L23/00 ,  H01L21/48 ,  H01L23/522

Abstract: A die seal ring and a manufacturing method thereof are provided. The die seal ring includes a substrate, a dielectric layer, and conductive layers. The dielectric layer is disposed on the substrate. The conductive layers are stacked on the substrate and located in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is disposed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is disposed between a sidewall of the second conductive portion and the dielectric layer. The die seal ring and the manufacturing method thereof can effectively prevent cracks generated during the die sawing process from damaging the circuit structure.

公开(公告)号：US20200058544A1

公开(公告)日：2020-02-20

申请号：US16134902

申请日：2018-09-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-How Chou ,  Tzu-Hao Fu ,  Tsung-Yin Hsieh ,  Chih-Sheng Chang ,  Shih-Chun Tsai ,  Kun-Chen Ho ,  Yang-Chou Lin

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A method for fabricating metal interconnect structure includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer on a substrate; forming a cap layer on the first metal interconnection; forming a second IMD layer on the cap layer; performing a first etching process to remove part of the second IMD layer for forming an opening; performing a plasma treatment process; and performing a second etching process to remove polymers from bottom of the opening.