公开(公告)号：US20250098273A1

公开(公告)日：2025-03-20

申请号：US18969201

申请日：2024-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Wen Zhang ,  Kun-Chen Ho ,  Chun-Lung Chen ,  Chung-Yi Chiu ,  Ming-Chou Lu

IPC: H01L29/49 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a gate structure on a substrate, a source/drain region adjacent to the gate structure, an interlayer dielectric (ILD) layer around the gate structure, a contact plug in the ILD layer and adjacent to the gate structure, an air gap around the contact plug, a barrier layer on and sealing the air gap, a metal layer on the barrier layer, a stop layer adjacent to the barrier layer and on the ILD layer, and an inter-metal dielectric (IMD) layer on the ILD layer. Preferably, bottom surfaces of the barrier layer and the stop layer are coplanar and top surfaces of the IMD layer and the barrier layer are coplanar.

公开(公告)号：US20250098271A1

公开(公告)日：2025-03-20

申请号：US18969172

申请日：2024-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Wen Zhang ,  Kun-Chen Ho ,  Chun-Lung Chen ,  Chung-Yi Chiu ,  Ming-Chou Lu

IPC: H01L29/49 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

公开(公告)号：US20210013401A1

公开(公告)日：2021-01-14

申请号：US16529779

申请日：2019-08-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pei-Jou Lee ,  Kun-Chen Ho ,  Hsuan-Hsu Chen ,  Chun-Lung Chen

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/02 ,  H01L27/22

Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate and a top electrode on the MTJ; forming a first inter-metal dielectric (IMD) layer around the MTJ and the top electrode; forming a stop layer on the first IMD layer; forming a second IMD layer on the stop layer; performing a first etching process to remove the second IMD layer and the stop layer; performing a second etching process to remove part of the top electrode; and forming a metal interconnection to connect to the top electrode.

公开(公告)号：US11882769B2

公开(公告)日：2024-01-23

申请号：US17239667

申请日：2021-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Bo-Yun Huang ,  Wen-Wen Zhang ,  Kun-Chen Ho

IPC: H01L43/02 ,  H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A magnetoresistive random access memory (MRAM) structure is provided in the present invention, including multiple MRAM cells, and an atomic layer deposition dielectric layer between and at outer sides of the MRAM cells, wherein the material of top electrode layer is titanium nitride, and the nitrogen percentage is greater than titanium percentage and further greater than oxygen percentage in the titanium nitride, and the nitrogen percentage gradually increases inward from the top surface of top electrode layer to a depth and then start to gradually decrease to a first level and then remains constant, and the titanium percentage gradually decreases inward from the top surface of top electrode layer to the depth and then start to gradually increase to a second level and then remains constant.

公开(公告)号：US20230411213A1

公开(公告)日：2023-12-21

申请号：US17868786

申请日：2022-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Wen Zhang ,  Ming-Chou Lu ,  Kun-Chen Ho ,  Dien-Yang Lu ,  Chun-Lung Chen ,  Chung-Yi Chiu

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/76832 ,  H01L21/7682 ,  H01L23/528 ,  H01L21/31116 ,  H01L29/66545

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming a contact etch stop layer (CESL) on the gate structure, forming an interlayer dielectric (ILD) layer on the CESL, forming a contact plug in the ILD layer and adjacent to the gate structure, forming a first stop layer on the ILD layer, and removing the first stop layer and the ILD layer around the gate structure to form an air gap exposing the CESL.

公开(公告)号：US20230070777A1

公开(公告)日：2023-03-09

申请号：US17984272

申请日：2022-11-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pei-Jou Lee ,  Kun-Chen Ho ,  Hsuan-Hsu Chen ,  Chun-Lung Chen

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate and a top electrode on the MTJ; forming a first inter-metal dielectric (IMD) layer around the MTJ and the top electrode; forming a stop layer on the first IMD layer; forming a second IMD layer on the stop layer; performing a first etching process to remove the second IMD layer and the stop layer; performing a second etching process to remove part of the top electrode; and forming a metal interconnection to connect to the top electrode.

公开(公告)号：US11387408B2

公开(公告)日：2022-07-12

申请号：US17131767

申请日：2020-12-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  Jing-Yin Jhang ,  I-Ming Tseng ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Kun-Chen Ho ,  Yi-Syun Chou ,  Chang-Min Li ,  Yi-Wei Tseng ,  Yu-Tsung Lai ,  Jun Xie

IPC: H01L29/82 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.

公开(公告)号：US20250098272A1

公开(公告)日：2025-03-20

申请号：US18969191

申请日：2024-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Wen Zhang ,  Kun-Chen Ho ,  Chun-Lung Chen ,  Chung-Yi Chiu ,  Ming-Chou Lu

IPC: H01L29/49 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

公开(公告)号：US20250079237A1

公开(公告)日：2025-03-06

申请号：US18950185

申请日：2024-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-How Chou ,  Tzu-Hao Fu ,  Tsung-Yin Hsieh ,  Chih-Sheng Chang ,  Shih-Chun Tsai ,  Kun-Chen Ho ,  Yang-Chou Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A metal interconnect structure includes a first metal interconnection in an inter-metal dielectric (IMD) layer on a substrate, a second metal interconnection on the first metal interconnection, and a cap layer between the first metal interconnection and the second metal interconnection. Preferably, a top surface of the first metal interconnection is even with a top surface of the IMD layer and the cap layer is made of conductive material.

公开(公告)号：US20240032439A1

公开(公告)日：2024-01-25

申请号：US18373295

申请日：2023-09-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  Jing-Yin Jhang ,  I-Ming Tseng ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Kun-Chen Ho ,  Yi-Syun Chou ,  Chang-Min Li ,  Yi-Wei Tseng ,  Yu-Tsung Lai ,  JUN XIE

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.