公开(公告)号：US10692875B2

公开(公告)日：2020-06-23

申请号：US16177812

申请日：2018-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wang Xiang ,  Chia-Ching Hsu ,  Chun-Sung Huang ,  Yung-Lin Tseng ,  Wei-Chang Liu ,  Shen-De Wang

IPC: H01L27/115 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/1157

Abstract: A memory structure including a substrate, at least one stacked gate structure, a first spacer conductive layer, and a first contact is provided. The stacked gate structure is located on the substrate and includes a control gate. The control gate extends in a first direction. The first spacer conductive layer is located on one sidewall of the control gate and is electrically insulated from the control gate. The first spacer conductive layer includes a first merged spacer portion and a first non-merged spacer portion. A line width of the first merged spacer portion is greater than a line width of the first non-merged spacer portion. The first contact is connected to the first merged spacer portion. The memory structure can have a larger process window of contact.

公开(公告)号：US09595588B1

公开(公告)日：2017-03-14

申请号：US15069331

申请日：2016-03-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Sung Huang ,  Ko-Chi Chen ,  Shen-De Wang

IPC: H01L29/788 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L29/42336 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11531

Abstract: A semiconductor device with embedded cell is provided. A silicon substrate has a first area with at least one first cell and a second area with at least one second cell. The first cell is positioned in the first area and formed in a trench of the silicon substrate, and the second cell is positioned in the second area and formed on the silicon substrate. The first cell includes a first dielectric layer formed on sidewalls and a bottom of the trench, a floating gate formed on the first dielectric layer and embedded in the trench, a second dielectric layer formed on the floating gate and embedded in the trench, and a control gate formed on the second dielectric layer and embedded in the trench, wherein the control gate is separated from the floating gate by the second dielectric layer.

Abstract translation: 提供具有嵌入式单元的半导体器件。 硅衬底具有具有至少一个第一单元的第一区域和具有至少一个第二单元的第二区域。 第一单元被定位在第一区域中并形成在硅衬底的沟槽中，并且第二单元被定位在第二区域中并形成在硅衬底上。 第一单元包括形成在沟槽的侧壁和底部上的第一介电层，形成在第一介电层上并嵌入在沟槽中的浮置栅极，形成在浮置栅极上并嵌入沟槽中的第二介电层，以及 控制栅极形成在第二介电层上并嵌入在沟槽中，其中控制栅极通过第二介电层与浮置栅极分离。

公开(公告)号：US09379128B1

公开(公告)日：2016-06-28

申请号：US14809342

申请日：2015-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Ko-Chi Chen ,  Shen-De Wang ,  Chia-Ching Hsu ,  Chun-Sung Huang ,  Wen-Peng Hsu

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L21/28 ,  H01L21/225

CPC classification number: H01L27/11568 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A split gate NVM device includes a semiconductor substrate, an ONO structure disposed on the semiconductor substrate, a first gate electrode disposed on the ONO structure, a second gate electrode disposed on the semiconductor substrate, adjacent to and insulated from the first gate electrode and the ONO structure, a first doping region with a first conductivity formed in the semiconductor substrate and adjacent to the ONO structure, a second doping region with the first conductivity formed in the semiconductor substrate and adjacent to the second gate electrode, and a third doping region with the first conductivity formed in the semiconductor substrate, disposed between the first doping region and the second doping region and adjacent to the ONO structure and the second gate electrode.

Abstract translation: 分路门NVM器件包括半导体衬底，设置在半导体衬底上的ONO结构，设置在ONO结构上的第一栅电极，设置在半导体衬底上的第二栅极，与第一栅电极相邻并绝缘， ONO结构，在半导体衬底中形成并与ONO结构相邻的具有第一导电性的第一掺杂区，在半导体衬底中形成并与第二栅电极相邻的具有第一导电性的第二掺杂区，以及第三掺杂区， 所述第一导电体形成在所述半导体衬底中，设置在所述第一掺杂区域和所述第二掺杂区域之间并且邻近所述ONO结构和所述第二栅电极。