公开(公告)号：US10699958B2

公开(公告)日：2020-06-30

申请号：US16116730

申请日：2018-08-29

Applicant: United Microelectronics Corp.

Inventor： Wei-Chang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wang Xiang ,  Wei Ta ,  Ling-Gang Fang ,  Shang Xue

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8239

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first gate, a gate dielectric layer, a pair of second gates, a first spacer, and a second spacer. The first gate is disposed on a substrate. The gate dielectric layer is disposed between the first gate and the substrate. The pair of second gates are disposed on the substrate and respectively located at two sides of the first gate, wherein top surfaces of the pair of second gates are higher than a top surface of the first gate. The first spacer is disposed on sidewalls of the pair of second gates protruding from the top surface of the first gate and covers the top surface of the first gate. The second spacer is disposed between the gate dielectric layer and the pair of second gates, between the first gate and the pair of second gates, and between the first spacer and the pair of second gates.

公开(公告)号：US20170338239A1

公开(公告)日：2017-11-23

申请号：US15161419

申请日：2016-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wei Ta ,  Wang Xiang ,  Yi-Shan Chiu

IPC: H01L27/11582 ,  H01L29/66

CPC classification number: H01L27/1157 ,  H01L29/40117 ,  H01L29/4234

Abstract: A semiconductor structure includes a substrate and a plurality of memory cells disposed on the substrate. Each memory cell includes a gate structure. The gate structures are spaced from each other by a spacing S. Each gate structure includes a dielectric layer and a gate electrode. The dielectric layer has an U-shape and defines an opening toward upside. The gate electrode is disposed in the opening. Each gate structure has a length L. A ratio of S/L is smaller than 1.

公开(公告)号：US20200043791A1

公开(公告)日：2020-02-06

申请号：US16116730

申请日：2018-08-29

Applicant: United Microelectronics Corp.

Inventor： Wei-Chang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wang Xiang ,  Wei Ta ,  Ling-Gang Fang ,  Shang Xue

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first gate, a gate dielectric layer, a pair of second gates, a first spacer, and a second spacer. The first gate is disposed on a substrate. The gate dielectric layer is disposed between the first gate and the substrate. The pair of second gates are disposed on the substrate and respectively located at two sides of the first gate, wherein top surfaces of the pair of second gates are higher than a top surface of the first gate. The first spacer is disposed on sidewalls of the pair of second gates protruding from the top surface of the first gate and covers the top surface of the first gate. The second spacer is disposed between the gate dielectric layer and the pair of second gates, between the first gate and the pair of second gates, and between the first spacer and the pair of second gates.

公开(公告)号：US10312249B2

公开(公告)日：2019-06-04

申请号：US15808019

申请日：2017-11-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chang Liu ,  Zhen Chen ,  Shen-De Wang ,  Chuan Sun ,  Wei Ta ,  Wang Xiang

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/266 ,  H01L29/788

Abstract: A method for forming a semiconductor device is provided, including providing a substrate having a first area comprising first semiconductor structures and a second area, wherein one of the first semiconductor structures comprises a memory gate made of a first polysilicon layer, and a second semiconductor structure comprises a second polysilicon layer disposed within the second area on the substrate; forming an organic material layer on the first semiconductor structures within the first area and on the second polysilicon layer within the second area; and patterning the organic material layer to form a patterned organic material layer, and the organic material layer exposing the memory gates of the first semiconductor structures, wherein a first pre-determined region and a second pre-determined region at the substrate are covered by the patterned organic material layer.

公开(公告)号：US20160042957A1

公开(公告)日：2016-02-11

申请号：US14454332

申请日：2014-08-07

Applicant: United Microelectronics Corp.

Inventor： Yuan-Hsiang Chang ,  Yi-Shan Chiu ,  Zhen Chen ,  Wei Ta ,  Wei-Chang Liu

IPC: H01L21/28 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L21/28282 ,  H01L27/11563 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor process is described. A semiconductor substrate having a memory area, a first device area and a second device area is provided. A patterned charge-trapping layer is formed on the substrate, covering the memory area and the second device area but exposing the first device area. A first gate oxide layer is formed in the first device area. The charge-trapping layer in the second device area is removed. A second gate oxide layer is formed in the second device area.

Abstract translation: 描述半导体工艺。 提供具有存储区域，第一设备区域和第二设备区域的半导体衬底。 图案化的电荷捕获层形成在衬底上，覆盖存储区域和第二器件区域，但暴露第一器件区域。 第一栅极氧化物层形成在第一器件区域中。 去除第二装置区域中的电荷捕获层。 第二栅极氧化层形成在第二器件区域中。

公开(公告)号：US10692875B2

公开(公告)日：2020-06-23

申请号：US16177812

申请日：2018-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wang Xiang ,  Chia-Ching Hsu ,  Chun-Sung Huang ,  Yung-Lin Tseng ,  Wei-Chang Liu ,  Shen-De Wang

IPC: H01L27/115 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/1157

Abstract: A memory structure including a substrate, at least one stacked gate structure, a first spacer conductive layer, and a first contact is provided. The stacked gate structure is located on the substrate and includes a control gate. The control gate extends in a first direction. The first spacer conductive layer is located on one sidewall of the control gate and is electrically insulated from the control gate. The first spacer conductive layer includes a first merged spacer portion and a first non-merged spacer portion. A line width of the first merged spacer portion is greater than a line width of the first non-merged spacer portion. The first contact is connected to the first merged spacer portion. The memory structure can have a larger process window of contact.

公开(公告)号：US09748256B2

公开(公告)日：2017-08-29

申请号：US14924525

申请日：2015-10-27

Applicant: United Microelectronics Corp.

Inventor： Wei-Chang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wang Xiang ,  Yi-Shan Chiu ,  Wei Ta

IPC: H01L29/788 ,  H01L27/11524 ,  H01L21/28

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: Provided is a semiconductor device including a memory gate structure and a select gate structure. The memory gate structure is closely adjacent to the select gate structure. Besides, an air gap encapsulated by an insulating layer is disposed between the memory gate structure and the select gate structure.

公开(公告)号：US20170077110A1

公开(公告)日：2017-03-16

申请号：US14924525

申请日：2015-10-27

Applicant: United Microelectronics Corp.

Inventor： Wei-Chang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wang Xiang ,  Yi-Shan Chiu ,  Wei Ta

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: Provided is a semiconductor device including a memory gate structure and a select gate structure. The memory gate structure is closely adjacent to the select gate structure. Besides, an air gap encapsulated by an insulating layer is disposed between the memory gate structure and the select gate structure.

Abstract translation: 提供了包括存储器栅极结构和选择栅极结构的半导体器件。 存储器栅极结构与选择栅极结构紧密相邻。 此外，由绝缘层封装的气隙设置在存储器栅极结构和选择栅极结构之间。

公开(公告)号：US09362125B2

公开(公告)日：2016-06-07

申请号：US14454332

申请日：2014-08-07

Applicant: United Microelectronics Corp.

Inventor： Yuan-Hsiang Chang ,  Yi-Shan Chiu ,  Zhen Chen ,  Wei Ta ,  Wei-Chang Liu

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L21/28282 ,  H01L27/11563 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor process is described. A semiconductor substrate having a memory area, a first device area and a second device area is provided. A patterned charge-trapping layer is formed on the substrate, covering the memory area and the second device area but exposing the first device area. A first gate oxide layer is formed in the first device area. The charge-trapping layer in the second device area is removed. A second gate oxide layer is formed in the second device area.

Abstract translation: 描述半导体工艺。 提供具有存储区域，第一设备区域和第二设备区域的半导体衬底。 图案化的电荷捕获层形成在衬底上，覆盖存储区域和第二器件区域，但暴露第一器件区域。 第一栅极氧化物层形成在第一器件区域中。 去除第二装置区域中的电荷捕获层。 第二栅极氧化层形成在第二器件区域中。