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    ALIGNMENT MARK STRUCTURE AND METHOD OF FABRICATING THE SAME
    11.
    发明申请
    ALIGNMENT MARK STRUCTURE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210249357A1

    公开(公告)日：2021-08-12

    申请号：US16786919

    申请日：2020-02-10

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kun-Ju Li ,  Jhih-Yuan Chen ,  Hsin-Jung Liu ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Fu-Chun Hsiao ,  Ji-Min Lin ,  Chun-Han Chen

    IPC: H01L23/544 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

    Abstract: An alignment mark structure includes a dielectric layer. A trench is embedded in the dielectric layer. An alignment mark fills up the trench, wherein the alignment mark includes a metal layer covering the trench. A first material layer covers and contacts the metal layer. A second material layer covers and contacts the first material layer. A third material layer covers and contacts the second material layer. The first material layer, the second material layer, and the third material layer are independently comprises silicon nitride, silicon oxide, tantalum-containing material, aluminum-containing material, titanium-containing material, or a low-k dielectric having a dielectric constant smaller than 2.7, and a reflectance of the first material layer is larger than a reflectance of the second material layer, the reflectance of the second material layer is larger than a reflectance of the third material layer.

    Manufacturing method of memory device
    12.
    发明授权
    Manufacturing method of memory device 有权

    公开(公告)号：US10804461B1

    公开(公告)日：2020-10-13

    申请号：US16517693

    申请日：2019-07-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Jung Liu ,  Kun-Ju Li ,  Ang Chan ,  Chau-Chung Hou ,  Yu-Lung Shih

    IPC: H01L21/00 ,  H01L43/12 ,  H01L43/02

    Abstract: A method for manufacturing a memory device is provided, the method includes the following steps: firstly, providing a dielectric layer, then simultaneously forming a contact window and an alignment mark trench in the dielectric layer, wherein the contact window exposes a lower metal line, then forming a conductive layer on the surface of the dielectric layer, in the contact window and in the alignment mark trench, performing a planarization step on the conductive layer, and leaving a residue in the alignment mark trench. Subsequently, a nitrogen plasma step (N2 plasma) is performed on the dielectric layer, a cleaning step is performed to remove the residue in the alignment mark trench, and a patterned magnetic tunneling junction, MTJ) film is laminated on the contact window.

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