公开(公告)号：US20240339331A1

公开(公告)日：2024-10-10

申请号：US18143076

申请日：2023-05-04

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chung-Fu Chang ,  Guang-Yu Lo ,  Chun-Tsen Lu

IPC分类号： H01L21/311 ,  H01L21/02 ,  H01L21/308 ,  H01L29/78

CPC分类号： H01L21/31144 ,  H01L21/02123 ,  H01L21/308 ,  H01L29/785 ,  H01L29/41791

摘要： A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising a medium-voltage (MV) region and a low-voltage (LV) region, forming a first gate structure and a second gate structure on the MV region and a second gate structure on the LV region, forming a patterned mask on the MV region as the patterned mask covers the first gate structure and the second gate structure and exposes the substrate between the first gate structure and the second gate structure, and then forming a first epitaxial layer between the first gate structure and the second gate structure.

公开(公告)号：US20240313046A1

公开(公告)日：2024-09-19

申请号：US18134555

申请日：2023-04-13

申请人： UNITED MICROELECTRONICS CORP.

发明人： Guang-Yu Lo ,  Chun-Tsen Lu ,  Chung-Fu Chang ,  Chih-Shan Wu ,  Yu-Hsiang Lin ,  Wei-Hao Chang

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

摘要： A method for fabricating a semiconductor device includes the steps of forming a fin-shaped structure on a substrate, forming a first trench and a second trench in the fin-shaped structure, forming a first dielectric layer in the first trench and the second trench, removing part of the first dielectric layer, forming a second dielectric layer in the first trench and the second trench to form a first single diffusion break (SDB) structure and a second SDB structure, and then forming a gate structure on the fin-shaped structure, the first SDB structure, and the second SDB structure.

公开(公告)号：US20230200088A1

公开(公告)日：2023-06-22

申请号：US18113070

申请日：2023-02-23

申请人： UNITED MICROELECTRONICS CORP.

发明人： Kun-Ju Li ,  Tai-Cheng Hou ,  Hsin-Jung Liu ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Chih-Yueh Li ,  Chun-Tsen Lu

IPC分类号： H10B61/00 ,  H01F41/34 ,  G11C11/16 ,  H01F10/32 ,  H10N50/01 ,  H10N50/80

CPC分类号： H10B61/00 ,  H01F41/34 ,  G11C11/161 ,  H01F10/3254 ,  H10N50/01 ,  H10N50/80

摘要： A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer. Preferably, the first ULK dielectric layer includes a first thickness, the passivation layer between the first MTJ and the second MTJ includes a second thickness, the passivation layer on top of the first MTJ includes a third thickness, and the second thickness is greater than the third thickness

公开(公告)号：US20180358266A1

公开(公告)日：2018-12-13

申请号：US15618131

申请日：2017-06-09

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chun-Hao Lin ,  Hsin-Yu Chen ,  Chun-Tsen Lu ,  Shou-Wei Hsieh

IPC分类号： H01L21/8234 ,  H01L21/02

CPC分类号： H01L21/823462 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02269 ,  H01L21/0228 ,  H01L21/823431

摘要： A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; forming a shallow trench isolation (STI) around the first fin-shaped structure; forming a first oxide layer on the first fin-shaped structure; and then forming a second oxide layer on the first oxide layer and the STI.

公开(公告)号：US20180138125A1

公开(公告)日：2018-05-17

申请号：US15853978

申请日：2017-12-26

申请人： UNITED MICROELECTRONICS CORP.

发明人： Kun-Ju Li ,  Kuo-Chin Hung ,  Min-Chuan Tsai ,  Wei-Chuan Tsai ,  Yi-Han Liao ,  Chun-Tsen Lu ,  Fu-Shou Tsai ,  Li-Chieh Hsu

IPC分类号： H01L23/528 ,  H01L29/417 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/5283 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/41758 ,  H01L29/66628 ,  H01L29/7833

摘要： A layout structure including a conductive structure is provided. The layout structure includes a dielectric layer formed on a substrate and a conductive structure formed in the dielectric layer. And the conductive structure further includes a barrier layer, a metal layer formed within the barrier layer, and a high resistive layer sandwiched in between the barrier layer and the metal layer.

公开(公告)号：US12009409B2

公开(公告)日：2024-06-11

申请号：US18118115

申请日：2023-03-06

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chung-Fu Chang ,  Kuan-Hung Chen ,  Guang-Yu Lo ,  Chun-Chia Chen ,  Chun-Tsen Lu

IPC分类号： H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/28202 ,  H01L29/511 ,  H01L29/7834 ,  H01L29/785

摘要： A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

公开(公告)号：US11004897B2

公开(公告)日：2021-05-11

申请号：US16531108

申请日：2019-08-04

申请人： UNITED MICROELECTRONICS CORP.

发明人： Kun-Ju Li ,  Tai-Cheng Hou ,  Hsin-Jung Liu ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Chih-Yueh Li ,  Chun-Tsen Lu

IPC分类号： H01L29/82 ,  H01L27/22 ,  H01L43/12 ,  H01F41/34 ,  G11C11/16 ,  H01F10/32 ,  H01L43/02

摘要： A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.

公开(公告)号：US20190140051A1

公开(公告)日：2019-05-09

申请号：US16222709

申请日：2018-12-17

申请人： United Microelectronics Corp.

发明人： Rung-Yuan Lee ,  Chun-Tsen Lu ,  Kuan-Hung Chen

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L29/417 ,  H01L29/786 ,  H01L21/308 ,  H01L29/423 ,  H01L21/306 ,  H01L23/535 ,  H01L29/41

CPC分类号： H01L29/0676 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/84 ,  H01L23/535 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/413 ,  H01L29/41733 ,  H01L29/41741 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/78642

摘要： A semiconductor device is provided. The semiconductor device includes a substrate, a semiconductor nanowire, a gate structure, a first metal nanowire and a second metal nanowire. The semiconductor nanowire is disposed vertically on the substrate. The gate structure surrounds a middle portion of the semiconductor nanowire. The first metal nanowire is located on a side of the semiconductor nanowire and is electronically connected to a lower portion of the semiconductor nanowire. The second metal nanowire is located on the other side of the semiconductor nanowire and is electronically connected to the gate structure.

公开(公告)号：US10204986B1

公开(公告)日：2019-02-12

申请号：US15783823

申请日：2017-10-13

申请人： United Microelectronics Corp.

发明人： Rung-Yuan Lee ,  Chun-Tsen Lu ,  Kuan-Hung Chen

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/41 ,  H01L29/417 ,  H01L23/535 ,  H01L21/306 ,  H01L29/66 ,  H01L21/308 ,  H01L29/786 ,  H01L21/84 ,  H01L27/12

摘要： A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a semiconductor nanowire, a gate structure, a first metal nanowire and a second metal nanowire. The semiconductor nanowire is disposed vertically on the substrate. The gate structure surrounds a middle portion of the semiconductor nanowire. The first metal nanowire is located on a side of the semiconductor nanowire and is electronically connected to a lower portion of the semiconductor nanowire. The second metal nanowire is located on the other side of the semiconductor nanowire and is electronically connected to the gate structure.

公开(公告)号：US20170040435A1

公开(公告)日：2017-02-09

申请号：US14840041

申请日：2015-08-30

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chun-Tsen Lu ,  Chien-Ming Lai ,  Lu-Sheng Chou ,  Ya-Huei Tsai ,  Ching-Hsiang Chiu ,  Yu-Tung Hsiao ,  Chen-Ming Huang ,  Kun-Ju Li ,  Yu-Ping Wang

IPC分类号： H01L29/66 ,  H01L29/49 ,  C22C32/00 ,  H01L29/423

CPC分类号： H01L29/66545 ,  B32B1/00 ,  B32B18/00 ,  C22C32/0068 ,  H01L21/28088 ,  H01L29/4238 ,  H01L29/4966 ,  H01L29/511

摘要： A semiconductor device is disclosed. The semiconductor device includes a substrate and a gate structure on the substrate. The gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, in which the top portion being a nitrogen rich portion, and the middle portion and the bottom portion being titanium rich portions.

摘要翻译： 公开了一种半导体器件。 半导体器件包括衬底和衬底上的栅极结构。 栅极结构包括在衬底上的高k电介质层和高k电介质层上的底部阻挡金属（BBM）层。 优选地，BBM层包括顶部，中间部分和底部，其中顶部是富氮部分，中部和底部是富钛部分。