-
公开(公告)号：US20200185597A1
公开(公告)日：2020-06-11
申请号：US16216969
申请日：2018-12-11
发明人： Kun-Ju Li , Hsin-Jung Liu , I-Ming Tseng , Chau-Chung Hou , Yu-Lung Shih , Fu-Chun Hsiao , Hui-Lin Wang , Tzu-Hsiang Hung , Chih-Yueh Li , Ang Chan , Jing-Yin Jhang
摘要： A memory device includes an insulation layer, a memory cell region and an alignment mark region are defined on the insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, the dielectric layer is disposed within the memory cell region and the alignment mark region, a conductive via plug disposed on the interconnection structure within the memory cell region, the conductive via plug has a concave top surface, an alignment mark trench penetrating the dielectric layer within the alignment mark region, a bottom electrode disposed on the conductive via plug within the memory cell region and disposed in the alignment mark trench within the alignment mark region, and a magnetic tunnel junction (MTJ) structure disposed on the bottom electrode within the memory cell region and disposed in the alignment mark trench within the alignment mark region.
-
公开(公告)号：US11145602B2
公开(公告)日：2021-10-12
申请号：US16786919
申请日：2020-02-10
发明人： Kun-Ju Li , Jhih-Yuan Chen , Hsin-Jung Liu , Chau-Chung Hou , Yu-Lung Shih , Ang Chan , Fu-Chun Hsiao , Ji-Min Lin , Chun-Han Chen
摘要： An alignment mark structure includes a dielectric layer. A trench is embedded in the dielectric layer. An alignment mark fills up the trench, wherein the alignment mark includes a metal layer covering the trench. A first material layer covers and contacts the metal layer. A second material layer covers and contacts the first material layer. A third material layer covers and contacts the second material layer. The first material layer, the second material layer, and the third material layer independently includes silicon nitride, silicon oxide, tantalum-containing material, aluminum-containing material, titanium-containing material, or a low-k dielectric having a dielectric constant smaller than 2.7, and a reflectance of the first material layer is larger than a reflectance of the second material layer, the reflectance of the second material layer is larger than a reflectance of the third material layer.
-
公开(公告)号：US11004897B2
公开(公告)日：2021-05-11
申请号：US16531108
申请日：2019-08-04
发明人： Kun-Ju Li , Tai-Cheng Hou , Hsin-Jung Liu , Fu-Yu Tsai , Bin-Siang Tsai , Chau-Chung Hou , Yu-Lung Shih , Ang Chan , Chih-Yueh Li , Chun-Tsen Lu
摘要： A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.
-
公开(公告)号：US20230200088A1
公开(公告)日：2023-06-22
申请号：US18113070
申请日：2023-02-23
发明人： Kun-Ju Li , Tai-Cheng Hou , Hsin-Jung Liu , Fu-Yu Tsai , Bin-Siang Tsai , Chau-Chung Hou , Yu-Lung Shih , Ang Chan , Chih-Yueh Li , Chun-Tsen Lu
CPC分类号： H10B61/00 , H01F41/34 , G11C11/161 , H01F10/3254 , H10N50/01 , H10N50/80
摘要： A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer. Preferably, the first ULK dielectric layer includes a first thickness, the passivation layer between the first MTJ and the second MTJ includes a second thickness, the passivation layer on top of the first MTJ includes a third thickness, and the second thickness is greater than the third thickness
-
公开(公告)号：US11482666B2
公开(公告)日：2022-10-25
申请号：US17023382
申请日：2020-09-17
发明人： Hsin-Jung Liu , Chau-Chung Hou , Ang Chan , Kun-Ju Li , Wen-Chin Lin
摘要： A semiconductor substrate is provided. The semiconductor substrate has thereon a first dielectric layer, at least one conductive pattern disposed in the first dielectric layer, and a second dielectric layer covering the first dielectric layer and the at least one conductive pattern. A via opening is formed in the second dielectric layer. The via opening exposes a portion of the at least one conductive pattern. A polish stop layer is conformally deposited on the second dielectric layer and within the via opening. A barrier layer is conformally deposited on the polish stop layer. A tungsten layer is conformally deposited on the barrier layer. The tungsten layer and the barrier layer are polished until the polish stop layer on the second dielectric layer is exposed, thereby forming a via plug in the via opening. A bottom electrode layer is conformally deposited on the second dielectric layer and the via plug.
-
公开(公告)号：US20220085284A1
公开(公告)日：2022-03-17
申请号：US17023382
申请日：2020-09-17
发明人： Hsin-Jung Liu , Chau-Chung Hou , Ang Chan , Kun-Ju Li , Wen-Chin Lin
摘要： A semiconductor substrate is provided. The semiconductor substrate has thereon a first dielectric layer, at least one conductive pattern disposed in the first dielectric layer, and a second dielectric layer covering the first dielectric layer and the at least one conductive pattern. A via opening is formed in the second dielectric layer. The via opening exposes a portion of the at least one conductive pattern. A polish stop layer is conformally deposited on the second dielectric layer and within the via opening. A barrier layer is conformally deposited on the polish stop layer. A tungsten layer is conformally deposited on the barrier layer. The tungsten layer and the barrier layer are polished until the polish stop layer on the second dielectric layer is exposed, thereby forming a via plug in the via opening. A bottom electrode layer is conformally deposited on the second dielectric layer and the via plug.
-
公开(公告)号：US12127413B2
公开(公告)日：2024-10-22
申请号：US18113070
申请日：2023-02-23
发明人： Kun-Ju Li , Tai-Cheng Hou , Hsin-Jung Liu , Fu-Yu Tsai , Bin-Siang Tsai , Chau-Chung Hou , Yu-Lung Shih , Ang Chan , Chih-Yueh Li , Chun-Tsen Lu
CPC分类号： H10B61/00 , G11C11/161 , H01F10/3254 , H01F41/34 , H10N50/01 , H10N50/80
摘要： A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer. Preferably, the first ULK dielectric layer includes a first thickness, the passivation layer between the first MTJ and the second MTJ includes a second thickness, the passivation layer on top of the first MTJ includes a third thickness, and the second thickness is greater than the third thickness
-
公开(公告)号：US20210249357A1
公开(公告)日：2021-08-12
申请号：US16786919
申请日：2020-02-10
发明人： Kun-Ju Li , Jhih-Yuan Chen , Hsin-Jung Liu , Chau-Chung Hou , Yu-Lung Shih , Ang Chan , Fu-Chun Hsiao , Ji-Min Lin , Chun-Han Chen
IPC分类号： H01L23/544 , H01L27/22 , H01L43/02 , H01L43/12
摘要： An alignment mark structure includes a dielectric layer. A trench is embedded in the dielectric layer. An alignment mark fills up the trench, wherein the alignment mark includes a metal layer covering the trench. A first material layer covers and contacts the metal layer. A second material layer covers and contacts the first material layer. A third material layer covers and contacts the second material layer. The first material layer, the second material layer, and the third material layer are independently comprises silicon nitride, silicon oxide, tantalum-containing material, aluminum-containing material, titanium-containing material, or a low-k dielectric having a dielectric constant smaller than 2.7, and a reflectance of the first material layer is larger than a reflectance of the second material layer, the reflectance of the second material layer is larger than a reflectance of the third material layer.
-
公开(公告)号：US10804461B1
公开(公告)日：2020-10-13
申请号：US16517693
申请日：2019-07-22
发明人： Hsin-Jung Liu , Kun-Ju Li , Ang Chan , Chau-Chung Hou , Yu-Lung Shih
摘要： A method for manufacturing a memory device is provided, the method includes the following steps: firstly, providing a dielectric layer, then simultaneously forming a contact window and an alignment mark trench in the dielectric layer, wherein the contact window exposes a lower metal line, then forming a conductive layer on the surface of the dielectric layer, in the contact window and in the alignment mark trench, performing a planarization step on the conductive layer, and leaving a residue in the alignment mark trench. Subsequently, a nitrogen plasma step (N2 plasma) is performed on the dielectric layer, a cleaning step is performed to remove the residue in the alignment mark trench, and a patterned magnetic tunneling junction, MTJ) film is laminated on the contact window.
-
公开(公告)号：US11621296B2
公开(公告)日：2023-04-04
申请号：US17223024
申请日：2021-04-06
发明人： Kun-Ju Li , Tai-Cheng Hou , Hsin-Jung Liu , Fu-Yu Tsai , Bin-Siang Tsai , Chau-Chung Hou , Yu-Lung Shih , Ang Chan , Chih-Yueh Li , Chun-Tsen Lu
摘要： A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.
-
-
-
-
-
-
-
-
-
搜索结果
13 条记录 (耗时 0.015 秒)
