公开(公告)号：US20190295896A1

公开(公告)日：2019-09-26

申请号：US15951192

申请日：2018-04-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Kuan-Hao Tseng ,  Yu-Hsiang Lin ,  Shih-Hung Tsai ,  Yu-Ting Tseng

IPC: H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L21/28 ,  H01L21/321

Abstract: A manufacturing method of an epitaxial fin-shaped structure includes the following steps. A substrate is provided. A recess is formed in the substrate. An epitaxial layer is formed on the substrate. The epitaxial layer is partly formed in the recess and partly formed outside the recess. The epitaxial layer has a dent formed on the top surface of the epitaxial layer, and the dent is formed corresponding to the recess in a thickness direction of the substrate. A nitride layer is conformally formed on the epitaxial layer. An oxide layer is formed on the nitride layer. A first planarization process is performed to remove a part of the oxide layer, and the first planarization process is stopped on the nitride layer. The epitaxial layer in the recess is patterned for forming at least one epitaxial fin-shaped structure.

公开(公告)号：US20190131183A1

公开(公告)日：2019-05-02

申请号：US15806277

申请日：2017-11-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Hao Tseng ,  Chien-Ting Lin ,  Shih-Hung Tsai ,  Po-Kuang Hsieh ,  Yu-Ting Tseng ,  Chueh-Fei Tai ,  Cheng-Ping Kuo

IPC: H01L21/8238 ,  H01L21/308 ,  H01L21/306 ,  H01L21/762 ,  H01L21/02 ,  H01L27/092 ,  H01L29/165 ,  H01L21/3065

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first well in the substrate on the first region and a second well in the substrate on the second region; removing part of the first well to form a first recess; and forming a first epitaxial layer in the first recess.

公开(公告)号：US12114508B2

公开(公告)日：2024-10-08

申请号：US17548607

申请日：2021-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Chun-Hsien Lin

IPC: H10B53/30

CPC classification number: H10B53/30

Abstract: A method for fabricating a semiconductor device includes the steps of forming a first inter-metal dielectric (IMD) layer on a substrate, forming a first trench and a second trench in the first IMD layer, forming a bottom electrode in the first trench and the second trench, forming a ferroelectric (FE) layer on the bottom electrode, and then forming a top electrode on the FE layer to form a ferroelectric random access memory (FeRAM).

公开(公告)号：US11705498B2

公开(公告)日：2023-07-18

申请号：US17185985

申请日：2021-02-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Ching-Wen Hung ,  Chun-Hsien Lin

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/1606 ,  H01L29/45 ,  H01L29/66045 ,  H01L29/78696

Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

公开(公告)号：US20220238677A1

公开(公告)日：2022-07-28

申请号：US17185985

申请日：2021-02-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Ching-Wen Hung ,  Chun-Hsien Lin

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66

Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

公开(公告)号：US20210057551A1

公开(公告)日：2021-02-25

申请号：US17090902

申请日：2020-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chang Lin ,  Bo-Han Huang ,  Chih-Chung Chen ,  Chun-Hsien Lin ,  Shih-Hung Tsai ,  Po-Kuang Hsieh

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/51

Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.

公开(公告)号：US20210050438A1

公开(公告)日：2021-02-18

申请号：US16578407

申请日：2019-09-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai

IPC: H01L29/778 ,  H01L29/66

Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed directly on the shallow recess.

公开(公告)号：US20190140068A1

公开(公告)日：2019-05-09

申请号：US16239541

申请日：2019-01-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Po-Kuang Hsieh ,  Yu-Ting Tseng ,  Cheng-Ping Kuo ,  Kuan-Hao Tseng

IPC: H01L29/51 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28 ,  H01L29/40

Abstract: A semiconductor device includes a metal gate on a substrate, a polysilicon layer on the metal gate, a hard mask on the polysilicon layer, and a source/drain region adjacent to two sides of the metal gate. Preferably, the metal gate includes a ferroelectric (FE) layer on the substrate, a work function metal layer on the FE layer, and a low resistance metal layer on the work function metal layer.

公开(公告)号：US20190019875A1

公开(公告)日：2019-01-17

申请号：US15678125

申请日：2017-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Po-Kuang Hsieh ,  Yu-Ting Tseng ,  Cheng-Ping Kuo ,  Kuan-Hao Tseng

IPC: H01L29/51 ,  H01L21/28 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming an interlayer dielectric (ILD) layer around the gate structure; removing the gate structure to form a first recess; forming ferroelectric (FE) layer in the first recess; forming a compressive layer on the FE layer; performing a thermal treatment process; removing the compressive layer; and forming a work function metal layer in the recess.

公开(公告)号：US20240431118A1

公开(公告)日：2024-12-26

申请号：US18822490

申请日：2024-09-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Chun-Hsien Lin

IPC: H10B53/30

Abstract: A method for fabricating a semiconductor device includes the steps of forming a first inter-metal dielectric (IMD) layer on a substrate, forming a first trench and a second trench in the first IMD layer, forming a bottom electrode in the first trench and the second trench, forming a ferroelectric (FE) layer on the bottom electrode, and then forming a top electrode on the FE layer to form a ferroelectric random access memory (FeRAM).