公开(公告)号：US20180226403A1

公开(公告)日：2018-08-09

申请号：US15445928

申请日：2017-02-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chi Chen ,  Chih-Chung Chen ,  An-Chi Liu ,  Chih-Yueh Li ,  Pei-Ching Yeh ,  Tsung-Chieh Yang

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of removing a fin structure includes providing a substrate. A fin structure extends from the substrate. A mask layer is disposed on a top surface of the fin structure. An organic dielectric layer covers the substrate, the fin structure and the mask layer. A first etching process is performed to entirely remove the mask layer by taking the organic dielectric layer as a mask. Then a second etching process is performed to remove the fin structure. The first etching process is preferably an anisotropic etching process, and the second etching process is an isotropic etching process.

公开(公告)号：US09117878B2

公开(公告)日：2015-08-25

申请号：US13710483

申请日：2012-12-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Keng-Jen Lin ,  Yu-Ren Wang ,  Chih-Chung Chen ,  Tsuo-Wen Lu ,  Tsai-Yu Wen

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/321

CPC classification number: H01L21/76232 ,  H01L21/02164 ,  H01L21/02219 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/32105

Abstract: A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate is provided and a patterned pad layer is formed on the semiconductor substrate so as to expose a portion of the semiconductor substrate. Then, the semiconductor substrate exposed from the patterned pad layer is etched away to form a trench inside the semiconductor substrate. A selectively-grown material layer is selectively formed on the surface of the trench, followed by filling a dielectric precursor material into the trench. Finally, a transformation process is carried out to concurrently transform the dielectric precursor material into a dielectric material and transform the selectively-grown material layer into an oxygen-containing amorphous material layer.

Abstract translation: 一种制造半导体结构的方法包括以下步骤。 首先，提供半导体衬底，并且在半导体衬底上形成图案化衬垫层以露出半导体衬底的一部分。 然后，从图案化衬垫层露出的半导体衬底被蚀刻掉以在半导体衬底内部形成沟槽。 在沟槽的表面上选择性地形成选择性生长的材料层，然后将电介质前体材料填充到沟槽中。 最后，进行转换处理以将电介质前体材料同时转变为电介质材料，并将选择性生长的材料层转变成含氧非晶材料层。

公开(公告)号：US20140162431A1

公开(公告)日：2014-06-12

申请号：US13710483

申请日：2012-12-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Keng-Jen Lin ,  Yu-Ren Wang ,  Chih-Chung Chen ,  Tsuo-Wen Lu ,  Tsai-Yu Wen

IPC: H01L21/762

CPC classification number: H01L21/76232 ,  H01L21/02164 ,  H01L21/02219 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/32105

Abstract: A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate is provided and a patterned pad layer is formed on the semiconductor substrate so as to expose a portion of the semiconductor substrate. Then, the semiconductor substrate exposed from the patterned pad layer is etched away to form a trench inside the semiconductor substrate. A selectively-grown material layer is selectively formed on the surface of the trench, followed by filling a dielectric precursor material into the trench. Finally, a transformation process is carried out to concurrently transform the dielectric precursor material into a dielectric material and transform the selectively-grown material layer into an oxygen-containing amorphous material layer.

Abstract translation: 一种制造半导体结构的方法包括以下步骤。 首先，提供半导体衬底，并且在半导体衬底上形成图案化衬垫层以露出半导体衬底的一部分。 然后，从图案化衬垫层露出的半导体衬底被蚀刻掉以在半导体衬底内部形成沟槽。 在沟槽的表面上选择性地形成选择性生长的材料层，然后将电介质前体材料填充到沟槽中。 最后，进行转换处理以将电介质前体材料同时转变为电介质材料，并将选择性生长的材料层转变成含氧非晶材料层。

公开(公告)号：US20230335622A1

公开(公告)日：2023-10-19

申请号：US18213903

申请日：2023-06-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chang Lin ,  Bo-Han Huang ,  Chih-Chung Chen ,  Chun-Hsien Lin ,  Shih-Hung Tsai ,  Po-Kuang Hsieh

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L29/66795 ,  H01L29/7851 ,  H01L21/02054 ,  H01L21/02052 ,  H01L29/517

Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.

公开(公告)号：US11735646B2

公开(公告)日：2023-08-22

申请号：US17090902

申请日：2020-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chang Lin ,  Bo-Han Huang ,  Chih-Chung Chen ,  Chun-Hsien Lin ,  Shih-Hung Tsai ,  Po-Kuang Hsieh

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/66795 ,  H01L21/02052 ,  H01L21/02054 ,  H01L29/517 ,  H01L29/7851

Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.

公开(公告)号：US20170345938A1

公开(公告)日：2017-11-30

申请号：US15681417

申请日：2017-08-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng-Hsu Liu ,  Jhen-cyuan Li ,  Chih-Chung Chen ,  Man-Ling Lu ,  Chung-Min Tsai ,  Yi-Wei Chen

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/7851 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  Y02E10/50

Abstract: A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The second semiconductor layer includes a recessed portion, the air gap is located in the recessed portion, and the recessed portion has an upwardly-opening acute angle in the range from about 10° to about 55°. The air gap may prevent current leakage. A FinFET device may be manufactured by first recessing and then epitaxially re-growing a source/drain fin, with the regrowth starting over a tubular air gap.

公开(公告)号：US09130014B2

公开(公告)日：2015-09-08

申请号：US14085811

申请日：2013-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Keng-Jen Lin ,  Yu-Ren Wang ,  Chien-Liang Lin ,  Tsuo-Wen Lu ,  Wei-Jen Chen ,  Chih-Chung Chen

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76237 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/32105 ,  H01L21/76205 ,  H01L21/76224

Abstract: A method for fabricating shallow trench isolation structure is disclosed. The method includes the steps of: (a) providing a substrate; (b) forming a trench in the substrate; (c) forming a silicon layer in the trench; and (d) performing an oxidation process to partially transform a surface of the silicon layer into an oxide layer.

Abstract translation: 公开了一种用于制造浅沟槽隔离结构的方法。 该方法包括以下步骤：（a）提供衬底; （b）在衬底中形成沟槽; （c）在沟槽中形成硅层; 和（d）进行氧化处理以将硅层的表面部分地转变为氧化物层。

公开(公告)号：US20220208612A1

公开(公告)日：2022-06-30

申请号：US17143179

申请日：2021-01-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chung Chen ,  Po-Chang Lin ,  Huang-Ren Wei ,  Wei-Lun Chou

IPC: H01L21/8234 ,  H01L21/266 ,  H01L21/311 ,  H01L21/02

Abstract: A method for forming a semiconductor device. A substrate having a first region and a second region surrounding the first region is provided. The first region includes a first active area and a first gate. A dummy pattern is disposed on the substrate within the second region around a perimeter of the first region. A resist pattern masks the second region and includes an opening that exposes the first region. An ion implantation process is performed to implant dopants through the opening into the first active area not covered by the first gate within the first region, thereby forming doped regions in the first active area. A resist stripping process is performed to remove the resist pattern by using a sulfuric acid-hydrogen peroxide mixture (SPM) solution at a temperature that is higher than or equal to 120˜190 degrees Celsius. The substrate is subjected to a cleaning process.

公开(公告)号：US20210057551A1

公开(公告)日：2021-02-25

申请号：US17090902

申请日：2020-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chang Lin ,  Bo-Han Huang ,  Chih-Chung Chen ,  Chun-Hsien Lin ,  Shih-Hung Tsai ,  Po-Kuang Hsieh

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/51

Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.

公开(公告)号：US20150140780A1

公开(公告)日：2015-05-21

申请号：US14085811

申请日：2013-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Keng-Jen Lin ,  Yu-Ren Wang ,  Chien-Liang Lin ,  Tsuo-Wen Lu ,  Wei-Jen Chen ,  Chih-Chung Chen

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76237 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/32105 ,  H01L21/76205 ,  H01L21/76224

Abstract: A method for fabricating shallow trench isolation structure is disclosed. The method includes the steps of: (a) providing a substrate; (b) forming a trench in the substrate; (c) forming a silicon layer in the trench; and (d) performing an oxidation process to partially transform a surface of the silicon layer into an oxide layer.

Abstract translation: 公开了一种用于制造浅沟槽隔离结构的方法。 该方法包括以下步骤：（a）提供衬底; （b）在衬底中形成沟槽; （c）在沟槽中形成硅层; 和（d）进行氧化处理以将硅层的表面部分地转变为氧化物层。