公开(公告)号：US09484422B2

公开(公告)日：2016-11-01

申请号：US14882462

申请日：2015-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao ,  Wen-Fang Lee ,  Shu-Wen Lin ,  Kuan-Chuan Chen

IPC: H01L29/76 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/08 ,  H01L21/266 ,  H01L21/28 ,  H01L21/265

CPC classification number: H01L29/42368 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28026 ,  H01L21/28158 ,  H01L21/2822 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/401 ,  H01L29/6659 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7834

Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.

Abstract translation: 本发明提供一种高压金属氧化物半导体（HVMOS）晶体管，其包括衬底，栅极电介质层，栅极电极和源极和漏极区域。 栅介质层设置在基板上，并且包括突出部分和凹陷部分，其中突出部分邻近凹部的两侧设置，并且具有大于凹部的厚度的厚度。 栅电极设置在栅介质层上。 因此，栅极电介质层的突出部分可以保持更高的击穿电压，从而保持电流不通过栅极泄漏。

公开(公告)号：US20160043193A1

公开(公告)日：2016-02-11

申请号：US14882462

申请日：2015-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao ,  Wen-Fang Lee ,  Shu-Wen Lin ,  Kuan-Chuan Chen

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/42368 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28026 ,  H01L21/28158 ,  H01L21/2822 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/401 ,  H01L29/6659 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7834

Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.

Abstract translation: 本发明提供一种高压金属氧化物半导体（HVMOS）晶体管，其包括衬底，栅极电介质层，栅极电极和源极和漏极区域。 栅介质层设置在基板上，并且包括突出部分和凹陷部分，其中突出部分邻近凹部的两侧设置，并且具有大于凹部的厚度的厚度。 栅电极设置在栅介质层上。 因此，栅极电介质层的突出部分可以保持更高的击穿电压，从而保持电流不通过栅极泄漏。

公开(公告)号：US20150287797A1

公开(公告)日：2015-10-08

申请号：US14273538

申请日：2014-05-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao ,  Wen-Fang Lee ,  Shu-Wen Lin ,  Kuan-Chuan Chen

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/08 ,  H01L21/266 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/42368 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28026 ,  H01L21/28158 ,  H01L21/2822 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/401 ,  H01L29/6659 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7834

Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.

Abstract translation: 本发明提供一种高压金属氧化物半导体（HVMOS）晶体管，其包括衬底，栅极电介质层，栅极电极和源极和漏极区域。 栅介质层设置在基板上，并且包括突出部分和凹陷部分，其中突出部分邻近凹部的两侧设置，并且具有大于凹部的厚度的厚度。 栅电极设置在栅介质层上。 因此，栅极电介质层的突出部分可以保持更高的击穿电压，从而保持电流不通过栅极泄漏。