公开(公告)号：US09111796B2

公开(公告)日：2015-08-18

申请号：US14158875

申请日：2014-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhen Chen ,  Shen-De Wang ,  Yi-Shan Chiu ,  Wei Cheng

IPC: H01L27/115 ,  H01L23/00 ,  H01L27/02 ,  H01L27/105

CPC classification number: H01L27/115 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11524

Abstract: A layout structure for memory devices includes a plurality of first gate patterns, a plurality of first landing pad patterns, a plurality of dummy patterns, a plurality of second landing pad patterns, and a plurality of second gate patterns. The first landing pad patterns are parallel with each other and electrically connected to the first gate patterns. The dummy patterns and the first landing pad patterns are alternately arranged, and the second landing pad patterns are respectively positioned in between one first landing pad pattern and one dummy pattern. The second gate patterns are electrically connected to the second landing pad patterns.

Abstract translation: 用于存储器件的布局结构包括多个第一栅极图案，多个第一着陆焊盘图案，多个虚设图案，多个第二着陆焊盘图案和多个第二栅极图案。 第一着陆焊盘图案彼此平行并电连接到第一栅极图案。 交替布置虚拟图案和第一着陆焊盘图案，并且第二着陆焊盘图案分别位于一个第一着陆焊盘图案和一个虚设图案之间。 第二栅极图案电连接到第二着陆焊盘图案。

公开(公告)号：US08921913B1

公开(公告)日：2014-12-30

申请号：US13923374

申请日：2013-06-21

Applicant: United Microelectronics Corp.

Inventor： Cheng-Yuan Hsu ,  Zhaobing Li ,  Chi Ren ,  Ching-Long Tsai ,  Wei Cheng

IPC: H01L21/336 ,  H01L21/28

CPC classification number: H01L21/28273 ,  H01L21/3212

Abstract: A floating gate forming process includes the following steps. A substrate containing active areas isolated from each other by isolation structures protruding from the substrate is provided. A first conductive material is formed to conformally cover the active areas and the isolation structure. An etch back process is performed on the first conductive material to respectively form floating gates separated from each other in the active areas.

Abstract translation: 浮栅形成工艺包括以下步骤。 提供了包含通过从衬底突出的隔离结构彼此隔离的有源区的衬底。 第一导电材料形成为保形地覆盖有源区域和隔离结构。 对第一导电材料进行回蚀处理，以分别形成在有源区域中彼此分离的浮动栅极。

公开(公告)号：US20140377945A1

公开(公告)日：2014-12-25

申请号：US13923374

申请日：2013-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yuan Hsu ,  ZHAOBING LI ,  CHI REN ,  Ching-Long Tsai ,  Wei Cheng

IPC: H01L21/28

CPC classification number: H01L21/28273 ,  H01L21/3212

Abstract: A floating gate forming process includes the following steps. A substrate containing active areas isolated from each other by isolation structures protruding from the substrate is provided. A first conductive material is formed to conformally cover the active areas and the isolation structure. An etch back process is performed on the first conductive material to respectively form floating gates separated from each other in the active areas.

Abstract translation: 浮栅形成工艺包括以下步骤。 提供了包含通过从衬底突出的隔离结构彼此隔离的有源区的衬底。 第一导电材料形成为保形地覆盖有源区域和隔离结构。 对第一导电材料进行回蚀处理，以分别形成在有源区域中彼此分离的浮动栅极。