公开(公告)号：US20150249158A1

公开(公告)日：2015-09-03

申请号：US14194957

申请日：2014-03-03

Applicant: United Microelectronics Corp.

Inventor： Wei Cheng ,  Hua-Kuo Lee ,  Ching-Long Tsai ,  Chi Ren ,  Cheng-Yuan Hsu

IPC: H01L29/788 ,  H01L21/3213 ,  H01L29/40

CPC classification number: H01L29/7883 ,  H01L27/11524 ,  H01L29/42328

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a first gate structure, a second gate electrode, a third gate electrode and a protective layer. The first gate structure comprises a first gate electrode disposed on the substrate and a first gate dielectric covering the first gate electrode. The second gate electrode is disposed on and electrically isolated from the first gate electrode. The first gate structure has an extending portion relative to the second gate electrode. The third gate electrode is disposed adjacent to and electrically isolated from the first gate electrode and the second gate electrode. The third gate has an extending portion between a lower surface of the protective layer and an upper surface of the extending portion of the first gate structure.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括衬底，第一栅极结构，第二栅电极，第三栅电极和保护层。 第一栅极结构包括设置在衬底上的第一栅极电极和覆盖第一栅电极的第一栅极电介质。 第二栅电极设置在第一栅电极上并与第一栅极电隔离。 第一栅极结构具有相对于第二栅电极的延伸部分。 第三栅电极设置成与第一栅电极和第二栅电极相邻并与之隔离。 第三栅极在保护层的下表面和第一栅极结构的延伸部分的上表面之间具有延伸部分。

公开(公告)号：US20150014761A1

公开(公告)日：2015-01-15

申请号：US13939186

申请日：2013-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yuan Hsu ,  ZHEN CHEN ,  CHI REN ,  Ching-Long Tsai ,  Wei Cheng ,  PING LIU

IPC: H01L21/28 ,  H01L29/423

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method for manufacturing a semiconductor device includes the following steps. At first, two gate stack layers are formed on a semiconductor substrate, wherein each of the gate stack layers includes a top surface and two side surfaces. A conductive material layer is deposited to conformally cover the top surface and the two side surfaces of each of the gate stack layers. Then, a cap layer is deposited to conformally cover the conductive material layer. Finally, the cap layer and the conductive material layer above the top surface of each of the gate stack layers are removed to leave the cap layer adjacent to the two side surfaces of each of the gate stack layers and covering a portion of the conductive material layer.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 首先，在半导体衬底上形成两个栅极堆叠层，其中每个栅极堆叠层包括顶表面和两个侧表面。 沉积导电材料层以共形地覆盖每个栅极堆叠层的顶表面和两个侧表面。 然后，沉积覆盖层以覆盖导电材料层。 最后，去除盖层和每个栅极堆叠层的顶表面上方的导电材料层，以使覆盖层与每个栅极叠层层的两个侧表面相邻并且覆盖导电材料层的一部分 。

公开(公告)号：US09401280B2

公开(公告)日：2016-07-26

申请号：US14288399

申请日：2014-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Duan Quan Liao ,  Wei Cheng ,  Yikun Chen ,  Ching Hwa Tey ,  Xiao Zhong Zhu

IPC: H01L21/28 ,  H01L27/115

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L27/11534

Abstract: A semiconductor process includes the following steps. A first gate is formed on a substrate, wherein the first gate includes a stacked gate on the substrate and a cap on the stacked gate. A spacer material is formed to conformally cover the first gate and the substrate. The spacer material is etched to form a spacer on a side of the first gate and a block on the other side of the first gate corresponding to the side. A material covers the substrate, the block, the first gate and the spacer, wherein the top surface of the material is a flat surface. The block, the spacer and the material are pulled down with the same pulling selectivity so that an assisting gate is formed from the block and a selective gate is formed from the spacer.

Abstract translation: 半导体工艺包括以下步骤。 第一栅极形成在衬底上，其中第一栅极包括衬底上的堆叠栅极和堆叠栅极上的帽。 形成间隔物材料以保形地覆盖第一栅极和衬底。 蚀刻间隔材料以在第一栅极的一侧上形成间隔物，并且在第一栅极的另一侧上对应于侧面的块。 材料覆盖基板，块，第一栅极和间隔件，其中材料的顶表面是平坦的表面。 块，间隔物和材料以相同的拉拔选择性被拉下，使得从块形成辅助栅极，并且由间隔物形成选择栅极。

公开(公告)号：US20150140800A1

公开(公告)日：2015-05-21

申请号：US14082200

申请日：2013-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei Cheng ,  Ming Sheng Xu ,  Duan Quan Liao ,  Yikun Chen ,  CHING HWA TEY

IPC: H01L21/28 ,  H01L21/8234

CPC classification number: H01L21/28132 ,  H01L21/28273 ,  H01L21/823468 ,  H01L27/11524

Abstract: A method of fabricating a semiconductor device includes the following steps. At least a first gate stack layer and at least a second gate stack layer protruding from a conductive layer on a substrate are provided. Subsequently, two spacers and a protective layer are formed on the conductive layer, and the two spacers and the protective layer jointly surround the protruded first gate stack layer and the protruded second gate stack layer. The two spacers and the protective layer are used as a mask to remove a part of the conductive layer. Afterwards, the two spacers and the protective layer are removed.

Abstract translation: 制造半导体器件的方法包括以下步骤。 提供至少一个第一栅堆叠层和至少一个从衬底上的导电层突出的第二栅堆叠层。 随后，在导电层上形成两个间隔物和保护层，两个间隔物和保护层共同围绕突出的第一栅叠层和突出的第二栅堆叠层。 将两个间隔物和保护层用作掩模以去除导电层的一部分。 之后，取下两个间隔物和保护层。

公开(公告)号：US09023726B1

公开(公告)日：2015-05-05

申请号：US14082200

申请日：2013-11-18

Applicant: United Microelectronics Corp.

Inventor： Wei Cheng ,  Ming Sheng Xu ,  Duan Quan Liao ,  Yikun Chen ,  Ching Hwa Tey

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L21/28132 ,  H01L21/28273 ,  H01L21/823468 ,  H01L27/11524

Abstract: A method of fabricating a semiconductor device includes the following steps. At least a first gate stack layer and at least a second gate stack layer protruding from a conductive layer on a substrate are provided. Subsequently, two spacers and a protective layer are formed on the conductive layer, and the two spacers and the protective layer jointly surround the protruded first gate stack layer and the protruded second gate stack layer. The two spacers and the protective layer are used as a mask to remove a part of the conductive layer. Afterwards, the two spacers and the protective layer are removed.

Abstract translation: 制造半导体器件的方法包括以下步骤。 提供至少一个第一栅堆叠层和至少一个从衬底上的导电层突出的第二栅堆叠层。 随后，在导电层上形成两个间隔物和保护层，两个间隔物和保护层共同围绕突出的第一栅叠层和突出的第二栅堆叠层。 将两个间隔物和保护层用作掩模以去除导电层的一部分。 之后，取下两个间隔物和保护层。

公开(公告)号：US20150348789A1

公开(公告)日：2015-12-03

申请号：US14288399

申请日：2014-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Duan Quan Liao ,  Wei Cheng ,  Yikun Chen ,  CHING HWA TEY ,  Xiao Zhong Zhu

IPC: H01L21/28

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L27/11534

Abstract: A semiconductor process includes the following steps. A first gate is formed on a substrate, wherein the first gate includes a stacked gate on the substrate and a cap on the stacked gate. A spacer material is formed to conformally cover the first gate and the substrate. The spacer material is etched to form a spacer on a side of the first gate and a block on the other side of the first gate corresponding to the side. A material covers the substrate, the block, the first gate and the spacer, wherein the top surface of the material is a flat surface. The block, the spacer and the material are pulled down with the same pulling selectivity so that an assisting gate is formed from the block and a selective gate is formed from the spacer.

Abstract translation: 半导体工艺包括以下步骤。 第一栅极形成在衬底上，其中第一栅极包括衬底上的堆叠栅极和堆叠栅极上的帽。 形成间隔物材料以保形地覆盖第一栅极和衬底。 蚀刻间隔材料以在第一栅极的一侧上形成间隔物，并且在第一栅极的另一侧上对应于侧面的块。 材料覆盖基板，块，第一栅极和间隔件，其中材料的顶表面是平坦的表面。 块，间隔物和材料以相同的拉拔选择性被拉下，使得从块形成辅助栅极，并且由间隔物形成选择栅极。

公开(公告)号：US20230099289A1

公开(公告)日：2023-03-30

申请号：US17502015

申请日：2021-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHEN CHEN ,  Wei Cheng ,  KOK WUN TAN ,  Shen-De Wang

IPC: H01L27/1157 ,  H01L29/06 ,  H01L27/11524

Abstract: A semiconductor memory structure includes a substrate having a device cell region and a contact forming region in proximity to the device cell region. A memory cell transistor is disposed within the device cell region. The memory cell transistor includes a gate and a charge storage structure between the gate and the substrate. The gate includes an extended portion within the contact forming region. A first spacer is disposed on a sidewall of the gate within the device cell region. A second spacer is disposed on a sidewall of the extended portion of the gate within the contact forming region. The second spacer is higher than the first spacer.

公开(公告)号：US20150206894A1

公开(公告)日：2015-07-23

申请号：US14158875

申请日：2014-01-20

Applicant: United Microelectronics Corp.

Inventor： Zhen Chen ,  Shen-De Wang ,  Yi-Shan Chiu ,  Wei Cheng

IPC: H01L27/115 ,  H01L23/00

CPC classification number: H01L27/115 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11524

Abstract: A layout structure for memory devices includes a plurality of first gate patterns, a plurality of first landing pad patterns, a plurality of dummy patterns, a plurality of second landing pad patterns, and a plurality of second gate patterns. The first landing pad patterns are parallel with each other and electrically connected to the first gate patterns. The dummy patterns and the first landing pad patterns are alternately arranged, and the second landing pad patterns are respectively positioned in between one first landing pad pattern and one dummy pattern. The second gate patterns are electrically connected to the second landing pad patterns.

Abstract translation: 用于存储器件的布局结构包括多个第一栅极图案，多个第一着陆焊盘图案，多个虚设图案，多个第二着陆焊盘图案和多个第二栅极图案。 第一着陆焊盘图案彼此平行并电连接到第一栅极图案。 交替布置虚拟图案和第一着陆焊盘图案，并且第二着陆焊盘图案分别位于一个第一着陆焊盘图案和一个虚设图案之间。 第二栅极图案电连接到第二着陆焊盘图案。

公开(公告)号：US20240081158A1

公开(公告)日：2024-03-07

申请号：US17950049

申请日：2022-09-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei Cheng ,  ZHEN CHEN ,  Shen-De Wang

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1675 ,  H01L27/2463 ,  H01L45/1233

Abstract: An RRAM structure includes a dielectric layer. A bottom electrode, a resistive switching layer and a top electrode are disposed from bottom to top on the dielectric layer. A spacer is disposed at sidewalls of the bottom electrode, the resistive switching layer and the top electrode. The spacer includes an L-shaped spacer and a sail-shaped spacer. The L-shaped spacer contacts the sidewall of the bottom electrode, the sidewall of the resistive switching layer and the sidewall of the top electrode. The sail-shaped spacer is disposed on the L-shaped spacer. A metal line is disposed on the top electrode and contacts the top electrode and the spacer.

公开(公告)号：US09431256B2

公开(公告)日：2016-08-30

申请号：US13939186

申请日：2013-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yuan Hsu ,  Zhen Chen ,  Chi Ren ,  Ching-Long Tsai ,  Wei Cheng ,  Ping Liu

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method for manufacturing a semiconductor device includes the following steps. At first, two gate stack layers are formed on a semiconductor substrate, wherein each of the gate stack layers includes a top surface and two side surfaces. A conductive material layer is deposited to conformally cover the top surface and the two side surfaces of each of the gate stack layers. Then, a cap layer is deposited to conformally cover the conductive material layer. Finally, the cap layer and the conductive material layer above the top surface of each of the gate stack layers are removed to leave the cap layer adjacent to the two side surfaces of each of the gate stack layers and covering a portion of the conductive material layer.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 首先，在半导体衬底上形成两个栅极堆叠层，其中每个栅极堆叠层包括顶表面和两个侧表面。 沉积导电材料层以共形地覆盖每个栅极堆叠层的顶表面和两个侧表面。 然后，沉积覆盖层以覆盖导电材料层。 最后，去除盖层和每个栅极堆叠层的顶表面上方的导电材料层，以使覆盖层与每个栅极叠层层的两个侧表面相邻并且覆盖导电材料层的一部分 。