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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200043791A1

    公开(公告)日：2020-02-06

    申请号：US16116730

    申请日：2018-08-29

    Applicant: United Microelectronics Corp.

    Inventor： Wei-Chang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wang Xiang ,  Wei Ta ,  Ling-Gang Fang ,  Shang Xue

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088

    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first gate, a gate dielectric layer, a pair of second gates, a first spacer, and a second spacer. The first gate is disposed on a substrate. The gate dielectric layer is disposed between the first gate and the substrate. The pair of second gates are disposed on the substrate and respectively located at two sides of the first gate, wherein top surfaces of the pair of second gates are higher than a top surface of the first gate. The first spacer is disposed on sidewalls of the pair of second gates protruding from the top surface of the first gate and covers the top surface of the first gate. The second spacer is disposed between the gate dielectric layer and the pair of second gates, between the first gate and the pair of second gates, and between the first spacer and the pair of second gates.

    Method for forming a semiconductor device
    2.
    发明授权
    Method for forming a semiconductor device 有权

    公开(公告)号：US10312249B2

    公开(公告)日：2019-06-04

    申请号：US15808019

    申请日：2017-11-09

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Chang Liu ,  Zhen Chen ,  Shen-De Wang ,  Chuan Sun ,  Wei Ta ,  Wang Xiang

    IPC: H01L27/11531 ,  H01L27/11521 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/266 ,  H01L29/788

    Abstract: A method for forming a semiconductor device is provided, including providing a substrate having a first area comprising first semiconductor structures and a second area, wherein one of the first semiconductor structures comprises a memory gate made of a first polysilicon layer, and a second semiconductor structure comprises a second polysilicon layer disposed within the second area on the substrate; forming an organic material layer on the first semiconductor structures within the first area and on the second polysilicon layer within the second area; and patterning the organic material layer to form a patterned organic material layer, and the organic material layer exposing the memory gates of the first semiconductor structures, wherein a first pre-determined region and a second pre-determined region at the substrate are covered by the patterned organic material layer.

    Semiconductor device and manufacturing method thereof
    4.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US09431256B2

    公开(公告)日：2016-08-30

    申请号：US13939186

    申请日：2013-07-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Cheng-Yuan Hsu ,  Zhen Chen ,  Chi Ren ,  Ching-Long Tsai ,  Wei Cheng ,  Ping Liu

    IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

    CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A method for manufacturing a semiconductor device includes the following steps. At first, two gate stack layers are formed on a semiconductor substrate, wherein each of the gate stack layers includes a top surface and two side surfaces. A conductive material layer is deposited to conformally cover the top surface and the two side surfaces of each of the gate stack layers. Then, a cap layer is deposited to conformally cover the conductive material layer. Finally, the cap layer and the conductive material layer above the top surface of each of the gate stack layers are removed to leave the cap layer adjacent to the two side surfaces of each of the gate stack layers and covering a portion of the conductive material layer.

    Abstract translation: 一种制造半导体器件的方法包括以下步骤。 首先，在半导体衬底上形成两个栅极堆叠层，其中每个栅极堆叠层包括顶表面和两个侧表面。 沉积导电材料层以共形地覆盖每个栅极堆叠层的顶表面和两个侧表面。 然后，沉积覆盖层以覆盖导电材料层。 最后，去除盖层和每个栅极堆叠层的顶表面上方的导电材料层，以使覆盖层与每个栅极叠层层的两个侧表面相邻并且覆盖导电材料层的一部分 。

    Semiconductor structure and layout structure for memory devices
    6.
    发明授权
    Semiconductor structure and layout structure for memory devices 有权
    存储器件的半导体结构和布局结构

    公开(公告)号：US09111796B2

    公开(公告)日：2015-08-18

    申请号：US14158875

    申请日：2014-01-20

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Zhen Chen ,  Shen-De Wang ,  Yi-Shan Chiu ,  Wei Cheng

    IPC: H01L27/115 ,  H01L23/00 ,  H01L27/02 ,  H01L27/105

    CPC classification number: H01L27/115 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11524

    Abstract: A layout structure for memory devices includes a plurality of first gate patterns, a plurality of first landing pad patterns, a plurality of dummy patterns, a plurality of second landing pad patterns, and a plurality of second gate patterns. The first landing pad patterns are parallel with each other and electrically connected to the first gate patterns. The dummy patterns and the first landing pad patterns are alternately arranged, and the second landing pad patterns are respectively positioned in between one first landing pad pattern and one dummy pattern. The second gate patterns are electrically connected to the second landing pad patterns.

    Abstract translation: 用于存储器件的布局结构包括多个第一栅极图案，多个第一着陆焊盘图案，多个虚设图案，多个第二着陆焊盘图案和多个第二栅极图案。 第一着陆焊盘图案彼此平行并电连接到第一栅极图案。 交替布置虚拟图案和第一着陆焊盘图案，并且第二着陆焊盘图案分别位于一个第一着陆焊盘图案和一个虚设图案之间。 第二栅极图案电连接到第二着陆焊盘图案。

    Flash cell and forming process thereof
    10.
    发明授权
    Flash cell and forming process thereof 有权
    闪电池及其成型工艺

    公开(公告)号：US09455322B1

    公开(公告)日：2016-09-27

    申请号：US14862118

    申请日：2015-09-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yi-Shan Chiu ,  Shen-De Wang ,  Weichang Liu ,  Wei Ta ,  Zhen Chen ,  Wang Xiang

    IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L29/788 ,  H01L27/115 ,  H01L29/51

    CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A flash cell forming process includes the following steps. A first gate is formed on a substrate. A first spacer is formed at a side of the first gate, where the first spacer includes a bottom part and a top part. The bottom part is removed, thereby an undercut being formed. A first selective gate is formed beside the first spacer and fills into the undercut. The present invention also provides a flash cell formed by said flash cell forming process. The flash cell includes a first gate, a first spacer and a first selective gate. The first gate is disposed on a substrate. The first spacer is disposed at a side of the first gate, where the first spacer has an undercut at a bottom part, and therefore exposes the substrate. The first selective gate is disposed beside the first spacer and extends into the undercut.

    Abstract translation: 闪光单元形成工艺包括以下步骤。 在基板上形成第一栅极。 第一间隔件形成在第一栅极的一侧，其中第一间隔件包括底部和顶部。 底部被去除，从而形成底切。 在第一间隔物旁边形成第一选择栅，并填入底切。 本发明还提供了一种由所述闪存单元形成工艺形成的闪光单元。 闪存单元包括第一栅极，第一间隔物和第一选择栅极。 第一栅极设置在基板上。 第一间隔件设置在第一栅极的一侧，其中第一间隔件在底部具有底切，因此露出基板。 第一选择栅设置在第一间隔物旁边并延伸到底切中。

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