公开(公告)号：US10177132B2

公开(公告)日：2019-01-08

申请号：US15088122

申请日：2016-04-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Yu-Lin Wang ,  Tzu-Feng Chang ,  Wei-Chi Lee

IPC: G06F17/50 ,  H01L27/02 ,  G03F1/36 ,  G11C11/419 ,  G11C11/412 ,  H01L27/11

Abstract: A layout pattern of a static random access memory, including a first inverter and a second inverter constituting a latch circuit. A first inner access transistor, a second inner access transistor, a first outer access transistor and a second outer access transistor are electrically connected to the latch circuit, wherein the first outer access transistor has a first gate length, the first inner access transistor has a second gate length, and the first gate length is different from the second gate length.

公开(公告)号：US10522551B2

公开(公告)日：2019-12-31

申请号：US15884063

申请日：2018-01-30

Applicant: United Microelectronics Corp.

Inventor： Chun-Hsien Huang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chang-Hung Chen ,  Shu-Ru Wang ,  Wei-Chi Lee ,  Chun-Yen Tseng

IPC: H01L27/11 ,  H01L27/092 ,  G11C11/41 ,  H01L23/522 ,  H01L27/02

Abstract: A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure has a first line terminal. The second circuit structure has a second line terminal. The first line terminal and the second line terminal are formed in a first circuit layer but separated by a gap. A conductive structure is forming in a second circuit layer above or below the first circuit layer, to electrically connect the first line terminal and the second line terminal.

公开(公告)号：US20170243861A1

公开(公告)日：2017-08-24

申请号：US15088122

申请日：2016-04-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Yu-Lin Wang ,  Tzu-Feng Chang ,  Wei-Chi Lee

IPC: H01L27/02 ,  G03F1/36 ,  G06F17/50 ,  G11C11/419

CPC classification number: H01L27/0207 ,  G03F1/36 ,  G06F17/5068 ,  G11C11/412 ,  G11C11/419 ,  H01L27/1104

Abstract: A layout pattern of a static random access memory, including a first inverter and a second inverter constituting a latch circuit. A first inner access transistor, a second inner access transistor, a first outer access transistor and a second outer access transistor are electrically connected to the latch circuit, wherein the first outer access transistor has a first gate length, the first inner access transistor has a second gate length, and the first gate length is different from the second gate length.

公开(公告)号：US20150348850A1

公开(公告)日：2015-12-03

申请号：US14289657

申请日：2014-05-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chi Lee ,  Yu-Lin Wang ,  Chung-Yuan Lee

IPC: H01L21/8238 ,  G03F1/00

CPC classification number: H01L21/823842 ,  G03F1/00

Abstract: A mask set includes a first mask and a second mask. The first mask includes geometric patterns. The second mask includes at least a strip-shaped pattern with a first edge and a second edge opposite to the first edge. The strip-shaped pattern has a centerline along a long axis of the strip-shaped pattern. The first edge includes inwardly displaced segments shifting towards the centerline and each of the inwardly displaced segments overlaps each of the geometric patterns.

Abstract translation: 掩模组包括第一掩模和第二掩模。 第一个面具包括几何图案。 第二掩模包括至少带状的图案，其具有第一边缘和与第一边缘相对的第二边缘。 带状图案具有沿着带状图案的长轴的中心线。 第一边缘包括朝向中心线移动的向内移位的段，并且每个向内移位的段与每个几何图案重叠。