公开(公告)号：US10985166B2

公开(公告)日：2021-04-20

申请号：US16177348

申请日：2018-10-31

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Hsu-Yang Wang ,  Ping-Cheng Hsu ,  Shih-Fang Tzou ,  Chin-Lung Lin ,  Yi-Hsiu Lee ,  Koji Taniguchi ,  Harn-Jiunn Wang ,  Tsung-Ying Tsai

IPC: H01L27/108 ,  H01L21/308 ,  H01L21/762

Abstract: A method for forming a memory device is disclosed, including providing a substrate, forming an isolation structure and plural active regions in the substrate, forming a plurality of island features on the substrate respectively covering two of the terminal portions of the active regions, using the island features as an etching mask to etch the substrate to perform a first etching process to define a first recessed region and plural island structures on the substrate. The island structures respectively comprise the two terminal portions of the active regions and the first recessed region comprises the central portions of the active regions.

公开(公告)号：US20160358813A1

公开(公告)日：2016-12-08

申请号：US14733930

申请日：2015-06-08

Applicant: United Microelectronics Corp.

Inventor： Harn-Jiunn Wang ,  Chin-Lung Lin ,  Yi-Hsiu Lee

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/0334 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/76229

Abstract: A method of forming trenches is provided. A first layer, a second layer and a third layer are formed on the substrate. A patterned third layer with a plurality of third trenches is formed. A spacer is formed on sidewalls of the third trenches, following by removing a portion of the patterned third layer between the third trenches. By using the spacer and the patterned third layer as a mask, a patterned second layer with a plurality of second trenches is formed. Next, the patterned third layer and the spacer are completely removed, and a block layer is formed on the patterned second layer, filling into the at least one second trench to separate said second trench into at least two parts. The first layer is patterned by using the patterned second layer and the block layer as a mask to form a patterned first layer with first trenches.

Abstract translation: 提供了一种形成沟槽的方法。 在基板上形成第一层，第二层和第三层。 形成具有多个第三沟槽的图案化第三层。 间隔件形成在第三沟槽的侧壁上，接着通过去除第三沟槽之间的图案化第三层的一部分。 通过使用间隔物和图案化的第三层作为掩模，形成具有多个第二沟槽的图案化的第二层。 接下来，完全去除图案化的第三层和间隔物，并且在图案化的第二层上形成阻挡层，填充到至少一个第二沟槽中，以将所述第二沟槽分成至少两个部分。 通过使用图案化的第二层和阻挡层作为掩模来对第一层进行构图，以形成具有第一沟槽的图案化的第一层。

公开(公告)号：US20150137369A1

公开(公告)日：2015-05-21

申请号：US14607051

申请日：2015-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Wen Fang ,  Chin-Lung Lin ,  Kuo-Chang Tien ,  Yi-Hsiu Lee ,  Chien-Hsiung Wang

IPC: H01L23/528 ,  G03F1/36 ,  H01L23/532 ,  G06F17/50 ,  H01L23/522

CPC classification number: H01L23/528 ,  G03F1/144 ,  G03F1/36 ,  G06F17/5068 ,  G06F17/5077 ,  G06T2207/30148 ,  H01L23/5226 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of optical proximity correction executed by a computer system for modifying line patterns includes the following steps. First, providing an integrated circuit layout with parallel line patterns and interconnect patterns disposed corresponding to the parallel line patterns. Then, using the computer to modify the integrated circuit layout based on a position of the interconnect patterns so as to generate a convex portion and a concave portion respectively on two sides of each of the parallel line patterns. Portions of the line pattern in front of and behind the convex portion and the concave portion are straight lines and have an identical critical dimension.

Abstract translation: 由计算机系统执行的用于修改线路图案的光学邻近校正的方法包括以下步骤。 首先，提供具有与平行线图案相对布置的平行线图案和互连图案的集成电路布局。 然后，使用计算机基于互连图案的位置来修改集成电路布局，以便分别在每个平行线图案的两侧上产生凸部和凹部。 在凸部和凹部之前和之后的线图案的部分是直线并且具有相同的临界尺寸。