公开(公告)号：US20240258311A1

公开(公告)日：2024-08-01

申请号：US18588942

申请日：2024-02-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Te-Hsin CHIU ,  Kam-Tou SIO ,  Shang-Wei FANG ,  Wei-Cheng LIN ,  Jiann-Tyng TZENG

IPC: H01L27/088 ,  G06F30/392 ,  H01L21/033 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  G06F30/392 ,  H01L21/0334 ,  H01L21/823431 ,  H01L29/0665 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Disclosed are semiconductor devices including a substrate, a first transistor formed over a first portion of the substrate, wherein the first transistor comprises a first nanosheet stack including N nanosheets and a second transistor over a second portion of the substrate, wherein the second transistor comprises a second nanosheet stack including M nanosheets, wherein N is different from M in which the first and second nanosheet stacks are formed on first and second substrate regions that are vertically offset from one another.

公开(公告)号：US12044961B2

公开(公告)日：2024-07-23

申请号：US17188140

申请日：2021-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pilsoo Kang ,  Wonchan Lee ,  Sangwook Kim ,  Sungyong Moon ,  Seunghune Yang ,  Jeeeun Jung

IPC: G03F1/70 ,  G03F1/24 ,  G03F1/36 ,  H01L21/033

CPC classification number: G03F1/70 ,  G03F1/24 ,  H01L21/0334 ,  G03F1/36

Abstract: A mask forming method includes providing preliminary mask data including a Manhattan path such as a quadrangle, a bar, a polygon or a combination thereof based on a layout. Mask data including a curvilinear shape is prepared by correcting the preliminary mask data through application of an elliptical function, a B-spline curve, or a combination thereof. A mask pattern is formed on a mask substrate based on the mask data.

公开(公告)号：US11942322B2

公开(公告)日：2024-03-26

申请号：US17226872

申请日：2021-04-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： An-Ren Zi ,  Chun-Chih Ho ,  Yahru Cheng ,  Ching-Yu Chang

IPC: H01L21/033 ,  G03F7/00 ,  G03F7/20 ,  H01L21/308

CPC classification number: H01L21/0334 ,  G03F7/70033 ,  H01L21/3083

Abstract: In a method of manufacturing a semiconductor device, a metallic photoresist layer is formed over a target layer to be patterned, the metallic photoresist layer is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern. The metallic photo resist layer is an alloy layer of two or more metal elements, and the selective exposure changes a phase of the alloy layer.

公开(公告)号：US11651968B2

公开(公告)日：2023-05-16

申请号：US17082535

申请日：2020-10-28

Applicant: SK hynix Inc.

Inventor： Ji Sok Lee ,  Sung Koo Lee ,  Jae Hee Sim

IPC: H01L21/3105 ,  H01L21/033

CPC classification number: H01L21/31051 ,  H01L21/0337 ,  H01L21/31058 ,  H01L21/0334

Abstract: A method for forming a planarization layer includes: providing a substrate including a trench; coating a pre-thinner over a surface of the trench; forming a gap-filling material in the trench; coating a post-thinner over the gap-filling material; and performing a spinning process to rotate the substrate.

公开(公告)号：US20230148156A1

公开(公告)日：2023-05-11

申请号：US18095260

申请日：2023-01-10

Applicant: Infineon Technologies AG

Inventor： Andreas Peter Meiser ,  Caspar Leendertz ,  Anton Mauder

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/808 ,  H01L29/739 ,  H01L29/40 ,  H01L29/423 ,  H01L21/308 ,  H01L21/31 ,  H01L21/04 ,  H01L21/311 ,  H01L21/426 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L29/1608 ,  H01L29/66924 ,  H01L29/0615 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/7397 ,  H01L29/0623 ,  H01L29/407 ,  H01L29/66348 ,  H01L29/4236 ,  H01L21/3083 ,  H01L21/31 ,  H01L21/0415 ,  H01L21/311 ,  H01L21/426 ,  H01L21/046 ,  H01L21/02019 ,  H01L21/0334

Abstract: A semiconductor component includes: a SiC semiconductor body; a trench extending from a first surface of the SiC semiconductor body into the SiC semiconductor body, the trench having a conductive connection structure, a structure width at a bottom of the trench, and a dielectric layer covering sidewalls of the trench; a shielding region along the bottom and having a central section which has a lateral first width; and a contact formed between the conductive connection structure and the shielding region. The conductive connection structure is electrically connected to a source electrode. In at least one doping plane extending approximately parallel to the bottom, a dopant concentration in the central section deviates by not more than 10% from a maximum value of the dopant concentration in the shielding region in the doping plane. The first width is less than the structure width and is at least 30% of the structure width.

公开(公告)号：US10083864B2

公开(公告)日：2018-09-25

申请号：US15405600

申请日：2017-01-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sean D. Burns ,  Lawrence A. Clevenger ,  Matthew E. Colburn ,  Sivananda K. Kanakasabapathy ,  Yann A. M. Mignot ,  Christopher J. Penny ,  Roger A. Quon ,  Nicole A. Saulnier

IPC: H01L21/768 ,  H01L21/033

CPC classification number: H01L21/76897 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/528

Abstract: A method for forming conductive lines comprises forming a hardmask on an insulator layer, a planarizing layer on the hardmask, and a hardmask on the planarizing layer, removing exposed portions of a layer of sacrificial mandrel material to form first and second sacrificial mandrels on the hardmask, and depositing a layer of spacer material in the gap, and over exposed portions of the first and second sacrificial mandrels and the hardmask. Portions of the layer of spacer material are removed to expose the first and second sacrificial mandrels. A filler material is deposited between the first and second sacrificial mandrels. A portion of the filler material is removed to expose the first and second sacrificial mandrels. Portions of the layer of spacer material are removed to expose portions of the hardmask. A trench is formed in the insulator layer, and the trench is filled with a conductive material.

公开(公告)号：US09989856B2

公开(公告)日：2018-06-05

申请号：US15080706

申请日：2016-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Woo Seo ,  Sang-Jin Kim ,  Jong-Seo Hong ,  Jong-Hoon Nah ,  Choon-Ho Song

IPC: G03F7/20 ,  H01L29/66 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213

CPC classification number: G03F7/2022 ,  G03F7/2002 ,  H01L21/0334 ,  H01L21/31144 ,  H01L21/32139 ,  H01L29/66545 ,  H01L29/66795

Abstract: Disclosed is a method of manufacturing semiconductor devices. A dummy gate structure is formed on a pattern area defined by an edge area of a substrate. An interlayer insulating layer pattern is formed to cover the pattern area and exposing the edge area of the substrate. A blocking pattern is formed on the interlayer insulating layer pattern such that the edge area of the substrate is covered with the blocking pattern and the pattern area of the substrate is exposed through the blocking pattern. A gate hole in the pattern area of the substrate in correspondence to the dummy gate structure, and a metal gate structure is formed in the gate hole. Accordingly, the edge area of the substrate is protected in the etching process and the deposition process of the replacement gate metal (RGM) process.

公开(公告)号：US09972502B2

公开(公告)日：2018-05-15

申请号：US14851768

申请日：2015-09-11

Applicant: LAM RESEARCH CORPORATION

Inventor： Jae Ho Lee ,  Changwoo Lee ,  Phil Friddle ,  Stefan Schmitz ,  Naveed Ansari ,  Michael Goss ,  Noel Sun

IPC: H01L21/311 ,  H01L21/302 ,  H01L21/461 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/033 ,  H01L21/02 ,  H01L21/283 ,  H01J37/32 ,  H01L21/308 ,  H01L21/28

CPC classification number: H01L21/31144 ,  H01J37/32366 ,  H01J2237/334 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/28141 ,  H01L21/283 ,  H01L21/3086 ,  H01L21/31116

Abstract: A method of performing a sidewall image transfer (SIT) process includes arranging a substrate within a substrate processing chamber, wherein the substrate includes a mandrel layer formed on the substrate and etching the mandrel layer to form a plurality of mandrels. The method further includes, without removing the substrate from within the substrate processing chamber and subsequent to etching the mandrel layer, depositing a thin spacer layer such that the thin spacer layer is formed on upper surfaces of the plurality of mandrels, sidewalls of the plurality of mandrels, and portions of the substrate between the sidewalls of the plurality of mandrels, subsequent to depositing the thin spacer layer, etching the thin spacer layer to remove the thin spacer layer from the upper surfaces of the mandrels and the portions of the substrate between the sidewalls of the plurality of mandrels such that only the thin spacer layer formed on the sidewalls of the plurality of mandrels remains, and, subsequent to etching the thin spacer layer from the upper surfaces of the mandrels and the portions of the substrate between the sidewalls of the plurality of mandrels, etching the plurality of mandrels to remove the plurality of mandrels from the substrate such that only the thin spacer layer formed on the sidewalls of the plurality of mandrels remains on the substrate.

公开(公告)号：US09859281B2

公开(公告)日：2018-01-02

申请号：US15219894

申请日：2016-07-26

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Miaomiao Wang ,  Tenko Yamashita

IPC: H01L27/092 ,  H01L21/308 ,  H01L29/66 ,  H01L21/306 ,  H01L21/033 ,  H01L21/3065 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/04 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0922 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7855

Abstract: A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed on sidewalls of the sacrificial mandrels. The sacrificial mandrels are removed to leave the spacers. A masking process leaves exposed a first set of spacers with a second set protected. In response to the masking process, a first fin etch process forms a first set of fins in the semiconductor layer via first set of spacers. The first set of fins has a vertical sidewall profile. Another masking process leaves exposed the second set of spacers with the first set of spacers and the first set of fins protected. In response to the other masking process, a second fin etch process forms a second set of fins in semiconductor layer using the second set of spacers. The second set of fins has a trapezoidal sidewall profile.

公开(公告)号：US20170275749A1

公开(公告)日：2017-09-28

申请号：US15512107

申请日：2015-10-05

Applicant: Japan Display Inc.

Inventor： Toshihiro SATO ,  Takeshi OOKAWARA

IPC: C23C14/04 ,  H01L51/50

CPC classification number: C23C14/042 ,  C23C8/04 ,  C23C14/24 ,  H01L21/0275 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/3086 ,  H01L51/0011 ,  H01L51/50 ,  H01L51/5012

Abstract: The purpose is providing a vapor deposition mask with high rigidity which can evaporate a uniform thickness film. A vapor deposition mask including a mask body having a main opening, a side surface of the main opening, an upper surface intersecting the side surface, and a lower surface opposing the upper surface, a first insulator contacting the lower surface, and a second insulator contacting the upper and side surfaces, wherein the first insulator includes a first region inside the main opening, and a first opening in the first region, the second insulator includes a second region inside the main opening, and a second opening in the second region, the mask body is sandwiched between the first and second insulators, and one of the first and second insulators includes a region located inside the main opening more centrally than the other and not overlapping with the other and the mask body.