公开(公告)号：US09524362B2

公开(公告)日：2016-12-20

申请号：US14692723

申请日：2015-04-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Harn-Jiunn Wang ,  Kuei-Chun Hung ,  Chih-Hsien Tang ,  Chin-Lung Lin

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G03F1/70 ,  G03F7/70433 ,  G03F7/70466

Abstract: A method of decomposing pattern layout for generating patterns on photomasks is disclosed. The method includes decomposing features of an integrated circuit layout into discrete patterns based on the relation between these features. The features include first features and second features. The first features are then classified into a first feature pattern and a second feature pattern, and the second features are classified into third, fourth, fifth and sixth feature patterns. The spacings of the second features in the fifth and sixth feature patterns are greater than a minimum exposure limits. Finally, the first feature pattern is outputted to a first photomask, the second feature pattern is outputted to a second photomask, the third and fifth feature patterns are outputted to a third photomask, and the fourth and sixth feature patterns are outputted to a fourth photomask.

Abstract translation: 公开了一种分解用于在光掩模上产生图案的图案布局的方法。 该方法包括基于这些特征之间的关系将集成电路布局的特征分解为离散模式。 功能包括第一个功能和第二个功能。 然后将第一特征分类为第一特征图案和第二特征图案，并且将第二特征分类为第三，第四，第五和第六特征图案。 第五和第六特征图案中的第二特征的间距大于最小暴露极限。 最后，将第一特征图案输出到第一光掩模，将第二特征图案输出到第二光掩模，将第三和第五特征图案输出到第三光掩模，并将第四和第六特征图案输出到第四光掩模 。

公开(公告)号：US09679901B1

公开(公告)日：2017-06-13

申请号：US15296955

申请日：2016-10-18

Applicant: United Microelectronics Corp. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Chien-Ting Ho ,  Le-Tien Jung ,  Shih-Fang Tzou ,  Chin-Lung Lin ,  Harn-Jiunn Wang

IPC: H01L21/762 ,  H01L27/108 ,  H01L29/06 ,  H01L21/461

CPC classification number: H01L27/10894 ,  H01L21/461 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/0649

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a plurality of active areas, and an isolation structure. The substrate has a device region and a peripheral region surrounding the device region. The active areas are located in the substrate in the device region. When viewed from above, the edges of the ends of the active areas adjacent to the boundary of the device region are aligned with each other, and the width of the ends of the active areas adjacent to the boundary of the device region is greater than the width of the other portions of the active areas. The isolation structure is disposed in the substrate and surrounds the active areas and is located in the peripheral region.

公开(公告)号：US09502285B1

公开(公告)日：2016-11-22

申请号：US14733930

申请日：2015-06-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Harn-Jiunn Wang ,  Chin-Lung Lin ,  Yi-Hsiu Lee

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/0334 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/76229

Abstract: A method of forming trenches is provided. A first layer, a second layer and a third layer are formed on the substrate. A patterned third layer with a plurality of third trenches is formed. A spacer is formed on sidewalls of the third trenches, following by removing a portion of the patterned third layer between the third trenches. By using the spacer and the patterned third layer as a mask, a patterned second layer with a plurality of second trenches is formed. Next, the patterned third layer and the spacer are completely removed, and a block layer is formed on the patterned second layer, filling into the at least one second trench to separate said second trench into at least two parts. The first layer is patterned by using the patterned second layer and the block layer as a mask to form a patterned first layer with first trenches.

Abstract translation: 提供了一种形成沟槽的方法。 在基板上形成第一层，第二层和第三层。 形成具有多个第三沟槽的图案化第三层。 间隔件形成在第三沟槽的侧壁上，接着通过去除第三沟槽之间的图案化第三层的一部分。 通过使用间隔物和图案化的第三层作为掩模，形成具有多个第二沟槽的图案化的第二层。 接下来，完全去除图案化的第三层和间隔物，并且在图案化的第二层上形成阻挡层，填充到至少一个第二沟槽中，以将所述第二沟槽分成至少两个部分。 通过使用图案化的第二层和阻挡层作为掩模来对第一层进行构图，以形成具有第一沟槽的图案化的第一层。

公开(公告)号：US11800702B2

公开(公告)日：2023-10-24

申请号：US17202359

申请日：2021-03-16

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Hsu-Yang Wang ,  Ping-Cheng Hsu ,  Shih-Fang Tzou ,  Chin-Lung Lin ,  Yi-Hsiu Lee ,  Koji Taniguchi ,  Harn-Jiunn Wang ,  Tsung-Ying Tsai

IPC: H01L27/108 ,  H10B12/00 ,  H01L21/308 ,  H01L21/762

CPC classification number: H10B12/482 ,  H01L21/3086 ,  H01L21/76224 ,  H10B12/053 ,  H10B12/34 ,  H10B12/485 ,  H10B12/488

Abstract: A method for forming a memory device includes the steps of providing a substrate, forming an isolation structure in the substrate to define a plurality of active regions in the substrate, the active regions respectively comprising two terminal portions and a central portion between the terminal portions, forming a plurality of island features on the substrate, wherein each of the island features covers two of the terminals portions respectively belonging to two of the active regions, performing a first etching process, using the island features as an etching mask to etch the substrate to define a plurality of island structures and a first recessed region surrounding the island structures on the substrate, and removing the island features to expose the island structures.

公开(公告)号：US10985166B2

公开(公告)日：2021-04-20

申请号：US16177348

申请日：2018-10-31

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Hsu-Yang Wang ,  Ping-Cheng Hsu ,  Shih-Fang Tzou ,  Chin-Lung Lin ,  Yi-Hsiu Lee ,  Koji Taniguchi ,  Harn-Jiunn Wang ,  Tsung-Ying Tsai

IPC: H01L27/108 ,  H01L21/308 ,  H01L21/762

Abstract: A method for forming a memory device is disclosed, including providing a substrate, forming an isolation structure and plural active regions in the substrate, forming a plurality of island features on the substrate respectively covering two of the terminal portions of the active regions, using the island features as an etching mask to etch the substrate to perform a first etching process to define a first recessed region and plural island structures on the substrate. The island structures respectively comprise the two terminal portions of the active regions and the first recessed region comprises the central portions of the active regions.

公开(公告)号：US20160358813A1

公开(公告)日：2016-12-08

申请号：US14733930

申请日：2015-06-08

Applicant: United Microelectronics Corp.

Inventor： Harn-Jiunn Wang ,  Chin-Lung Lin ,  Yi-Hsiu Lee

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/0334 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/76229

Abstract: A method of forming trenches is provided. A first layer, a second layer and a third layer are formed on the substrate. A patterned third layer with a plurality of third trenches is formed. A spacer is formed on sidewalls of the third trenches, following by removing a portion of the patterned third layer between the third trenches. By using the spacer and the patterned third layer as a mask, a patterned second layer with a plurality of second trenches is formed. Next, the patterned third layer and the spacer are completely removed, and a block layer is formed on the patterned second layer, filling into the at least one second trench to separate said second trench into at least two parts. The first layer is patterned by using the patterned second layer and the block layer as a mask to form a patterned first layer with first trenches.

Abstract translation: 提供了一种形成沟槽的方法。 在基板上形成第一层，第二层和第三层。 形成具有多个第三沟槽的图案化第三层。 间隔件形成在第三沟槽的侧壁上，接着通过去除第三沟槽之间的图案化第三层的一部分。 通过使用间隔物和图案化的第三层作为掩模，形成具有多个第二沟槽的图案化的第二层。 接下来，完全去除图案化的第三层和间隔物，并且在图案化的第二层上形成阻挡层，填充到至少一个第二沟槽中，以将所述第二沟槽分成至少两个部分。 通过使用图案化的第二层和阻挡层作为掩模来对第一层进行构图，以形成具有第一沟槽的图案化的第一层。

公开(公告)号：US20210202492A1

公开(公告)日：2021-07-01

申请号：US17202359

申请日：2021-03-16

Applicant: United Microelectronics Corp. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Hsu-Yang Wang ,  Ping-Cheng Hsu ,  Shih-Fang Tzou ,  Chin-Lung Lin ,  Yi-Hsiu Lee ,  Koji Taniguchi ,  Harn-Jiunn Wang ,  Tsung-Ying Tsai

IPC: H01L27/108 ,  H01L21/308 ,  H01L21/762

Abstract: A method for forming a memory device includes the steps of providing a substrate, forming an isolation structure in the substrate to define a plurality of active regions in the substrate, the active regions respectively comprising two terminal portions and a central portion between the terminal portions, forming a plurality of island features on the substrate, wherein each of the island features covers two of the terminals portions respectively belonging to two of the active regions, performing a first etching process, using the island features as an etching mask to etch the substrate to define a plurality of island structures and a first recessed region surrounding the island structures on the substrate, and removing the island features to expose the island structures.

公开(公告)号：US20190189620A1

公开(公告)日：2019-06-20

申请号：US16177348

申请日：2018-10-31

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Hsu-Yang Wang ,  Ping-Cheng Hsu ,  Shih-Fang Tzou ,  Chin-Lung Lin ,  Yi-Hsiu Lee ,  Koji Taniguchi ,  Harn-Jiunn Wang ,  Tsung-Ying Tsai

IPC: H01L27/108 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L27/10885 ,  H01L21/3086 ,  H01L21/76224 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891

Abstract: A method for forming a memory device is disclosed, including providing a substrate, forming an isolation structure and plural active regions in the substrate, forming a plurality of island features on the substrate respectively covering two of the terminal portions of the active regions, using the island features as an etching mask to etch the substrate to perform a first etching process to define a first recessed region and plural island structures on the substrate. The island structures respectively comprise the two terminal portions of the active regions and the first recessed region comprises the central portions of the active regions.

公开(公告)号：US20160314233A1

公开(公告)日：2016-10-27

申请号：US14692723

申请日：2015-04-21

Applicant: United Microelectronics Corp.

Inventor： Harn-Jiunn Wang ,  Kuei-Chun Hung ,  Chih-Hsien Tang ,  Chin-Lung Lin

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G03F1/70 ,  G03F7/70433 ,  G03F7/70466

Abstract: A method of decomposing pattern layout for generating patterns on photomasks is disclosed. The method includes decomposing features of an integrated circuit layout into discrete patterns based on the relation between these features. The features include first features and second features. The first features are then classified into a first feature pattern and a second feature pattern, and the second features are classified into third, fourth, fifth and sixth feature patterns. The spacings of the second features in the fifth and sixth feature patterns are greater than a minimum exposure limits. Finally, the first feature pattern is outputted to a first photomask, the second feature pattern is outputted to a second photomask, the third and fifth feature patterns are outputted to a third photomask, and the fourth and sixth feature patterns are outputted to a fourth photomask.

Abstract translation: 公开了一种分解用于在光掩模上产生图案的图案布局的方法。 该方法包括基于这些特征之间的关系将集成电路布局的特征分解为离散模式。 功能包括第一个功能和第二个功能。 然后将第一特征分类为第一特征图案和第二特征图案，并且将第二特征分类为第三，第四，第五和第六特征图案。 第五和第六特征图案中的第二特征的间距大于最小暴露极限。 最后，将第一特征图案输出到第一光掩模，将第二特征图案输出到第二光掩模，将第三和第五特征图案输出到第三光掩模，并将第四和第六特征图案输出到第四光掩模 。

公开(公告)号：US10969687B2

公开(公告)日：2021-04-06

申请号：US16209871

申请日：2018-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Harn-Jiunn Wang ,  Kai-Ming Liu ,  Chin-Lung Lin ,  Yi-Hsiu Lee

IPC: G03F7/20 ,  H01L21/3213 ,  H01L21/027

Abstract: A method for forming patterns is provided in the present invention. The process includes the steps of using a first mask to perform a first exposure process to a photoresist, using a second mask to perform a second exposure process to the photoresist, wherein the corners of the second opening patterns in the second mask and the corners of the first opening patterns in the first mask overlap each other, and performing a development process to remove the unexposed portions of the photoresist in the two exposure processes to form staggered hole patterns therein.