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公开(公告)号：US09524362B2
公开(公告)日：2016-12-20
申请号：US14692723
申请日：2015-04-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Harn-Jiunn Wang , Kuei-Chun Hung , Chih-Hsien Tang , Chin-Lung Lin
IPC: G06F17/50
CPC classification number: G06F17/5068 , G03F1/70 , G03F7/70433 , G03F7/70466
Abstract: A method of decomposing pattern layout for generating patterns on photomasks is disclosed. The method includes decomposing features of an integrated circuit layout into discrete patterns based on the relation between these features. The features include first features and second features. The first features are then classified into a first feature pattern and a second feature pattern, and the second features are classified into third, fourth, fifth and sixth feature patterns. The spacings of the second features in the fifth and sixth feature patterns are greater than a minimum exposure limits. Finally, the first feature pattern is outputted to a first photomask, the second feature pattern is outputted to a second photomask, the third and fifth feature patterns are outputted to a third photomask, and the fourth and sixth feature patterns are outputted to a fourth photomask.
Abstract translation: 公开了一种分解用于在光掩模上产生图案的图案布局的方法。 该方法包括基于这些特征之间的关系将集成电路布局的特征分解为离散模式。 功能包括第一个功能和第二个功能。 然后将第一特征分类为第一特征图案和第二特征图案，并且将第二特征分类为第三，第四，第五和第六特征图案。 第五和第六特征图案中的第二特征的间距大于最小暴露极限。 最后，将第一特征图案输出到第一光掩模，将第二特征图案输出到第二光掩模，将第三和第五特征图案输出到第三光掩模，并将第四和第六特征图案输出到第四光掩模 。
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2.发明授权Method of optical proximity correction for modifying line patterns and integrated circuits with line patterns modified by the same 有权用于修改线图案的光学邻近校正方法和由其修改的线图案的集成电路的方法公开(公告)号：US08977988B2
公开(公告)日：2015-03-10
申请号：US13859718
申请日：2013-04-09
Applicant: United Microelectronics Corp.
Inventor： Kuan-Wen Fang , Chin-Lung Lin , Kuo-Chang Tien , Yi-Hsiu Lee , Chien-Hsiung Wang
CPC classification number: H01L23/528 , G03F1/144 , G03F1/36 , G06F17/5068 , G06F17/5077 , G06T2207/30148 , H01L23/5226 , H01L23/53271 , H01L2924/0002 , H01L2924/00
Abstract: A method of optical proximity correction executed by a computer system and integrated circuit layout formed by the same, the step of optical proximity correction comprises: providing an integrated circuit layout with a plurality of parallel line patterns, wherein one side of at least one line pattern is provided with a convex portion; and modifying the integrated circuit layout by forming a concave portion corresponding to the convex portion at the other side of the line pattern.
Abstract translation: 由计算机系统执行的光学邻近校正方法和由其形成的集成电路布局的方法，光学邻近校正步骤包括：提供具有多条平行线图案的集成电路布局，其中至少一条线图案的一侧 设置有凸部; 以及通过在所述线图案的另一侧形成与所述凸部对应的凹部来修改所述集成电路布局。
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公开(公告)号：US20140331191A1
公开(公告)日：2014-11-06
申请号：US13887377
申请日：2013-05-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Tsung-Yeh Wu , Chin-Lung Lin , Yao-Jen Fan , Wei-Han Chien , Chia-Chun Tsai
IPC: G06F17/50
CPC classification number: G06F17/5081 , G03F1/36
Abstract: A method of correcting assist features includes the following steps. At first, a first layout pattern is received by a computer system, and the first layout pattern is split into a plurality of first regions. Subsequently, a plurality of assist features are added into the first layout pattern to form a second layout pattern, wherein at least one of the assist features neighboring any one of the edges of the first regions is defined as a selected pattern. Then, the second layout pattern is split into a plurality of second regions. Afterwards, a check step is performed on the second region including the selected pattern, and the second layout pattern is corrected to form a corrected second layout pattern.
Abstract translation: 一种校正辅助功能的方法包括以下步骤。 首先，由计算机系统接收第一布局图案，并且将第一布局图案分割成多个第一区域。 随后，将多个辅助特征添加到第一布局图案中以形成第二布局图案，其中与第一区域的任何边缘相邻的辅助特征中的至少一个被定义为所选择的图案。 然后，第二布局图案被分割成多个第二区域。 然后，对包括所选择的图案的第二区域执行检查步骤，并校正第二布局图案以形成校正的第二布局图案。
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4.发明申请公开(公告)号：US20140304666A1
公开(公告)日：2014-10-09
申请号：US13859718
申请日：2013-04-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Kuan-Wen Fang , Chin-Lung Lin , Kuo-Chang Tien , Yi-Hsiu Lee , Chien-Hsiung Wang
IPC: G06F17/50
CPC classification number: H01L23/528 , G03F1/144 , G03F1/36 , G06F17/5068 , G06F17/5077 , G06T2207/30148 , H01L23/5226 , H01L23/53271 , H01L2924/0002 , H01L2924/00
Abstract: A method of optical proximity correction executed by a computer system and integrated circuit layout formed by the same, the step of optical proximity correction comprises: providing an integrated circuit layout with a plurality of parallel line patterns, wherein one side of at least one line pattern is provided with a convex portion; and modifying the integrated circuit layout by forming a concave portion corresponding to the convex portion at the other side of the line pattern.
Abstract translation: 由计算机系统执行的光学邻近校正方法和由其形成的集成电路布局的方法，光学邻近校正步骤包括：提供具有多条平行线图案的集成电路布局，其中至少一条线图案的一侧 设置有凸部; 以及通过在所述线图案的另一侧形成与所述凸部对应的凹部来修改所述集成电路布局。
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公开(公告)号：US09679901B1
公开(公告)日：2017-06-13
申请号：US15296955
申请日：2016-10-18
Inventor： Ying-Chiao Wang , Chien-Ting Ho , Le-Tien Jung , Shih-Fang Tzou , Chin-Lung Lin , Harn-Jiunn Wang
IPC: H01L21/762 , H01L27/108 , H01L29/06 , H01L21/461
CPC classification number: H01L27/10894 , H01L21/461 , H01L21/762 , H01L21/76224 , H01L29/0649
Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a plurality of active areas, and an isolation structure. The substrate has a device region and a peripheral region surrounding the device region. The active areas are located in the substrate in the device region. When viewed from above, the edges of the ends of the active areas adjacent to the boundary of the device region are aligned with each other, and the width of the ends of the active areas adjacent to the boundary of the device region is greater than the width of the other portions of the active areas. The isolation structure is disposed in the substrate and surrounds the active areas and is located in the peripheral region.
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Patent Agency Ranking
公开(公告)号：US09502285B1
公开(公告)日：2016-11-22
申请号：US14733930
申请日：2015-06-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Harn-Jiunn Wang , Chin-Lung Lin , Yi-Hsiu Lee
IPC: H01L21/768
CPC classification number: H01L21/76816 , H01L21/0334 , H01L21/3083 , H01L21/31144 , H01L21/76229
Abstract: A method of forming trenches is provided. A first layer, a second layer and a third layer are formed on the substrate. A patterned third layer with a plurality of third trenches is formed. A spacer is formed on sidewalls of the third trenches, following by removing a portion of the patterned third layer between the third trenches. By using the spacer and the patterned third layer as a mask, a patterned second layer with a plurality of second trenches is formed. Next, the patterned third layer and the spacer are completely removed, and a block layer is formed on the patterned second layer, filling into the at least one second trench to separate said second trench into at least two parts. The first layer is patterned by using the patterned second layer and the block layer as a mask to form a patterned first layer with first trenches.
Abstract translation: 提供了一种形成沟槽的方法。 在基板上形成第一层，第二层和第三层。 形成具有多个第三沟槽的图案化第三层。 间隔件形成在第三沟槽的侧壁上，接着通过去除第三沟槽之间的图案化第三层的一部分。 通过使用间隔物和图案化的第三层作为掩模，形成具有多个第二沟槽的图案化的第二层。 接下来，完全去除图案化的第三层和间隔物，并且在图案化的第二层上形成阻挡层，填充到至少一个第二沟槽中，以将所述第二沟槽分成至少两个部分。 通过使用图案化的第二层和阻挡层作为掩模来对第一层进行构图，以形成具有第一沟槽的图案化的第一层。
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公开(公告)号：US20160048072A1
公开(公告)日：2016-02-18
申请号：US14504401
申请日：2014-10-01
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Hsien Tang , Yao-Jen Fan , Chin-Lung Lin
IPC: G03F1/70
CPC classification number: G03F1/70 , G03F7/70433 , G03F7/70466 , G06F17/5081
Abstract: A layout pattern decomposition method includes following steps. A layout pattern is received. The layout pattern includes a plurality of features, and an edge-to-edge space is respectively defined in between two adjacent features. A sum of a width of the edge-to-edge space and a width of the feature on a left side of the edge-to-edge space and a sum of the width of the edge-to-edge space and a width of the feature on a right side of the edge-to-edge space are respectively calculated. The sums and a predetermined value are respectively compared. When any one of the sums is smaller than the predetermined value, the two features on the two sides of the edge-to-edge space are colored by a first color and alternatively a second color. The features including the first color are assigned to a first pattern and the features including the second color to a second pattern.
Abstract translation: 布局模式分解方法包括以下步骤。 接收到布局模式。 布局图案包括多个特征，并且在两个相邻特征之间分别限定边缘到边缘空间。 边缘至边缘空间的宽度和边缘至边缘空间的左侧上的特征的宽度的总和以及边缘至边缘空间的宽度和宽度之和 分别计算边缘到边缘空间右侧的特征。 分别对和值和预定值进行比较。 当总和中的任何一个小于预定值时，边缘到边缘空间的两侧上的两个特征被第一颜色和第二颜色着色。 包括第一颜色的特征被分配给第一图案，并且将包括第二颜色的特征分配给第二图案。
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公开(公告)号：US09009633B2
公开(公告)日：2015-04-14
申请号：US13887377
申请日：2013-05-06
Applicant: United Microelectronics Corp.
Inventor： Tsung-Yeh Wu , Chin-Lung Lin , Yao-Jen Fan , Wei-Han Chien , Chia-Chun Tsai
CPC classification number: G06F17/5081 , G03F1/36
Abstract: A method of correcting assist features includes the following steps. At first, a first layout pattern is received by a computer system, and the first layout pattern is split into a plurality of first regions. Subsequently, a plurality of assist features are added into the first layout pattern to form a second layout pattern, wherein at least one of the assist features neighboring any one of the edges of the first regions is defined as a selected pattern. Then, the second layout pattern is split into a plurality of second regions. Afterwards, a check step is performed on the second region including the selected pattern, and the second layout pattern is corrected to form a corrected second layout pattern.
Abstract translation: 一种校正辅助功能的方法包括以下步骤。 首先，由计算机系统接收第一布局图案，并且将第一布局图案分割成多个第一区域。 随后，将多个辅助特征添加到第一布局图案中以形成第二布局图案，其中与第一区域的任何边缘相邻的辅助特征中的至少一个被定义为所选择的图案。 然后，第二布局图案被分割成多个第二区域。 然后，对包括所选择的图案的第二区域执行检查步骤，并校正第二布局图案以形成校正的第二布局图案。
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公开(公告)号：US11800702B2
公开(公告)日：2023-10-24
申请号：US17202359
申请日：2021-03-16
Inventor： Hsu-Yang Wang , Ping-Cheng Hsu , Shih-Fang Tzou , Chin-Lung Lin , Yi-Hsiu Lee , Koji Taniguchi , Harn-Jiunn Wang , Tsung-Ying Tsai
IPC: H01L27/108 , H10B12/00 , H01L21/308 , H01L21/762
CPC classification number: H10B12/482 , H01L21/3086 , H01L21/76224 , H10B12/053 , H10B12/34 , H10B12/485 , H10B12/488
Abstract: A method for forming a memory device includes the steps of providing a substrate, forming an isolation structure in the substrate to define a plurality of active regions in the substrate, the active regions respectively comprising two terminal portions and a central portion between the terminal portions, forming a plurality of island features on the substrate, wherein each of the island features covers two of the terminals portions respectively belonging to two of the active regions, performing a first etching process, using the island features as an etching mask to etch the substrate to define a plurality of island structures and a first recessed region surrounding the island structures on the substrate, and removing the island features to expose the island structures.
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公开(公告)号：US10985166B2
公开(公告)日：2021-04-20
申请号：US16177348
申请日：2018-10-31
Inventor： Hsu-Yang Wang , Ping-Cheng Hsu , Shih-Fang Tzou , Chin-Lung Lin , Yi-Hsiu Lee , Koji Taniguchi , Harn-Jiunn Wang , Tsung-Ying Tsai
IPC: H01L27/108 , H01L21/308 , H01L21/762
Abstract: A method for forming a memory device is disclosed, including providing a substrate, forming an isolation structure and plural active regions in the substrate, forming a plurality of island features on the substrate respectively covering two of the terminal portions of the active regions, using the island features as an etching mask to etch the substrate to perform a first etching process to define a first recessed region and plural island structures on the substrate. The island structures respectively comprise the two terminal portions of the active regions and the first recessed region comprises the central portions of the active regions.
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