公开(公告)号：US20230246023A1

公开(公告)日：2023-08-03

申请号：US18298322

申请日：2023-04-10

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou

IPC: H01L27/06 ,  H01L27/12 ,  H01L21/768 ,  H01L23/522 ,  H01L21/762 ,  H01L23/528

CPC classification number: H01L27/0688 ,  H01L21/76251 ,  H01L21/76898 ,  H01L23/528 ,  H01L23/5226 ,  H01L27/1203

Abstract: A method for fabricating a semiconductor device is provided, including following steps. Providing a staked layer of a semiconductor layer, a buried oxide layer and a silicon layer. Forming a silicon-based device layer comprising the silicon layer on the buried oxide layer. Forming a first interconnection layer over the silicon-based device layer. Forming a semiconductor-based device layer comprising the semiconductor layer on the buried oxide layer. Forming a second interconnection layer over the semiconductor-based device layer.

公开(公告)号：US10686011B2

公开(公告)日：2020-06-16

申请号：US15909592

申请日：2018-03-01

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou

IPC: H01L27/24 ,  H01L27/22 ,  H01L29/786 ,  H01L27/11502

Abstract: A semiconductor device integrated with memory device includes a substrate, having a first side and a second side. A transistor circuit layer is disposed over the substrate at the first side. An interconnect structure layer is disposed over the transistor circuit layer with electric connection to form a circuit route. A memory cell layer is disposed over the interconnect structure layer or over a second side of the substrate, in connection to the circuit route. The memory cell layer includes a plurality of memory cells, and a cell structure of the memory cells includes an oxide semiconductor field effect transistor and a memory element.

公开(公告)号：US20190273119A1

公开(公告)日：2019-09-05

申请号：US15909592

申请日：2018-03-01

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou

IPC: H01L27/24 ,  H01L29/786 ,  H01L27/22

Abstract: A semiconductor device integrated with memory device includes a substrate, having a first side and a second side. A transistor circuit layer is disposed over the substrate at the first side. An interconnect structure layer is disposed over the transistor circuit layer with electric connection to form a circuit route. A memory cell layer is disposed over the interconnect structure layer or over a second side of the substrate, in connection to the circuit route. The memory cell layer includes a plurality of memory cells, and a cell structure of the memory cells includes an oxide semiconductor field effect transistor and a memory element.

公开(公告)号：US20190035887A1

公开(公告)日：2019-01-31

申请号：US16152240

申请日：2018-10-04

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou

IPC: H01L29/06 ,  H01L27/12 ,  H01L21/762 ,  H01L23/535 ,  H01L49/02 ,  H01L21/84 ,  H01L29/66

Abstract: A semiconductor device is provided. The semiconductor device includes an insulating structure and a dielectric structure. The insulating structure is disposed on a substrate and has a plurality of openings. The dielectric structure is disposed on the insulating structure and extending into the plurality of openings.

公开(公告)号：US10109474B1

公开(公告)日：2018-10-23

申请号：US15603046

申请日：2017-05-23

Applicant: United Microelectronics Corp.

Inventor： Wei-Jin Wang ,  Zhi-Biao Zhou

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/60

Abstract: A method for fabricating handling wafer includes providing a substrate, having a front side and a back side. The front side of the substrate is disposed on a supporting pin. A first oxide layer is formed surrounding the substrate. A portion of the first oxide layer is removed to expose the front side of the substrate. An alignment mark is formed on the front side of the substrate.

公开(公告)号：US20170098712A1

公开(公告)日：2017-04-06

申请号：US14874546

申请日：2015-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Biao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Su Xing ,  Tien-Yu Hsieh

IPC: H01L29/786 ,  H01L27/108 ,  H01L27/115 ,  H01L29/66 ,  H01L49/02

CPC classification number: H01L27/1052 ,  H01L27/108 ,  H01L27/115 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/66742 ,  H01L29/7869

Abstract: A semiconductor transistor device includes an oxide semiconductor layer having an active surface, a source electrode, a drain electrode, a gate electrode and a control capacitor. The gate electrode, the source electrode and the drain electrode are directly in contact with the active surface. The gate electrode is disposed between the drain electrode and the source electrode. The gate electrode, the source electrode and the drain electrode are separated from each other. The control capacitor is electrically connected to the gate electrode through a connection.

公开(公告)号：US12112981B2

公开(公告)日：2024-10-08

申请号：US17679133

申请日：2022-02-24

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/522 ,  H01L27/12

CPC classification number: H01L21/7682 ,  H01L21/76897 ,  H01L23/5222 ,  H01L27/1207

Abstract: A semiconductor device is provided. The semiconductor device includes a device substrate, having a device structure layer and a buried dielectric layer, wherein the buried dielectric layer is disposed on a semiconductor layer of the device structure layer and the device substrate comprises a device structure. A metal layer is disposed on the buried dielectric layer and surrounded by a first inter-layer dielectric (ILD) layer. A region of the metal layer has a plurality of openings. The buried dielectric layer has an air gap under and exposing the region of the metal layer with the openings, wherein the air gap is located above the device structure in the device substrate. A second ILD layer is disposed on the metal layer and sealing the air gap at the openings of the metal layer.

公开(公告)号：US11569355B1

公开(公告)日：2023-01-31

申请号：US17470801

申请日：2021-09-09

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

Abstract: A method of manufacturing a memory structure including following steps is provided. Two gate stack structures are formed on a substrate. A conductive material layer is conformally formed on the two gate stack structures. The conductive material layer includes two protrusions located on the two gate stack structures. Hard mask spacers are formed on two sides of each of the two protrusions. A first etching process is performed to remove a portion of the conductive material layer by using the hard mask spacers as a mask. A second etching process is performed to completely remove the hard mask spacers. Then, a third etching process is performed on the conductive material layer to form a first conductive spacer and a second conductive spacer located on one side and the other side of the two gate stack structures and to form a conductive layer located between the two gate stack structures.

公开(公告)号：US11289368B2

公开(公告)日：2022-03-29

申请号：US16884081

申请日：2020-05-27

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L27/12

Abstract: A semiconductor device is provided. The semiconductor device includes a device substrate, having a device structure layer and a buried dielectric layer, wherein the buried dielectric layer is disposed on a semiconductor layer of the device structure layer. A metal layer is disposed on the buried dielectric layer and surrounded by a first inter-layer dielectric (ILD) layer. A region of the metal layer has a plurality of openings. The buried dielectric layer has an air gap under and exposing the region of the metal layer with the openings. A second ILD layer is disposed on the metal layer and sealing the air gap at the openings of the metal layer.

公开(公告)号：US10515876B1

公开(公告)日：2019-12-24

申请号：US16159789

申请日：2018-10-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Biao Zhou

IPC: H01L21/4763 ,  H01L23/482 ,  H01L23/64 ,  H01L21/768 ,  H01L23/528 ,  H01L21/764 ,  H01L23/522

Abstract: A method for forming a semiconductor device includes: providing a structure having a first stop layer formed above a substrate, a first dielectric layer formed on the first stop layer, a second stop layer formed on the first dielectric layer, and conductive lines formed in the first dielectric layer and spaced apart from each other; forming a first dummy layer on the second stop layer; patterning the first dummy layer to form a first patterned dummy layer; forming a second dummy layer on the first dummy layer to form a first trench; etching back the second dummy layer and the first patterned dummy layer to form a second trench, wherein the second trench is self-aligned with the first trench. The second trench extends downwardly to the first dielectric layer and forms an opening at the second stop layer.