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    Reconfigurable network-on-chip security architecture
    12.
    发明授权
    Reconfigurable network-on-chip security architecture 有权

    公开(公告)号：US11593298B2

    公开(公告)日：2023-02-28

    申请号：US17092703

    申请日：2020-11-09

    Applicant: University of Florida Research Foundation, Inc.

    Inventor： Prabhat Kumar Mishra ,  Thelijjagoda S N Charles

    IPC: G06F1/24 ,  G06F9/00 ,  G06F15/78 ,  G06F21/55 ,  G06F21/71

    Abstract: The present disclosure presents an exemplary tier-based reconfigurable security architecture that can adapt to different use-case scenarios by selecting security tiers and configure parameters in each security tier based on system requirements. An exemplary system comprises a security agent that is configured to monitor system characteristics of embedded components on a system-on-chip and communicate a status of the system characteristics to a reconfigurable service engine integrated on the system-on-chip, such that the reconfigurable service engine is configured to activate one of a plurality of tiers of security based at least upon the status of the system characteristics communicated.

    HARDWARE TROJAN DETECTION USING REINFORCEMENT LEARNING
    13.
    发明申请
    HARDWARE TROJAN DETECTION USING REINFORCEMENT LEARNING 有权

    公开(公告)号：US20220188415A1

    公开(公告)日：2022-06-16

    申请号：US17543940

    申请日：2021-12-07

    Applicant: University of Florida Research Foundation, Inc.

    Inventor： Prabhat Kumar Mishra ,  Zhixin Pan

    IPC: G06F21/55 ,  G06N20/00

    Abstract: The present disclosure provides systems and methods for test pattern generation to detect a hardware Trojan. One such method includes determining, by a computing device, a set of initial test patterns to activate the hardware Trojan within an integrated circuit design; evaluating nodes of the integrated circuit design and assigning a rareness attribute value and a testability attribute value associated with respective nodes of the integrated circuit design; and generating a set of additional test patterns to activate the hardware Trojan within the integrated circuit design using a reinforcement learning model. The set of initial test patterns is applied as an input along with rareness attribute values and testability attribute values associated with the nodes of the integrated circuit, and the reinforcement learning model is trained with a stochastic learning scheme to identify optimal test patterns for triggering nodes of the integrated circuit design.

    TRIGGER ACTIVATION BY REPEATED MAXIMAL CLIQUE SAMPLING
    14.
    发明申请
    TRIGGER ACTIVATION BY REPEATED MAXIMAL CLIQUE SAMPLING 有权

    公开(公告)号：US20210004459A1

    公开(公告)日：2021-01-07

    申请号：US16893701

    申请日：2020-06-05

    Applicant: University of Florida Research Foundation, Inc.

    Inventor： Prabhat Kumar Mishra ,  Yangdi Lyu

    IPC: G06F21/55

    Abstract: An exemplary method for generating a test vector to activate a Trojan triggering condition includes the operations of obtaining a design graph representation of an electronic circuit; constructing a satisfiability graph from the design graph representation, wherein the satisfiability graph includes a set of vertices representing rare signals of the electronic circuit and satisfiability connections between the vertices; finding a plurality of maximal satisfiable cliques in the satisfiability graph, wherein a maximal satisfiable clique corresponds to a triggering condition for a payload of the electronic circuit; generating a test vector for each of the maximal satisfiable cliques; and performing a test for the presence of a hardware Trojan circuit in the electronic circuit using the generated test vectors as input signals.

    SCALABLE DETECTION OF HARDWARE TROJANS USING ATPG-BASED ACTIVATION OF RARE EVENTS
    15.
    发明申请
    SCALABLE DETECTION OF HARDWARE TROJANS USING ATPG-BASED ACTIVATION OF RARE EVENTS 有权

    公开(公告)号：US20250086288A1

    公开(公告)日：2025-03-13

    申请号：US18794774

    申请日：2024-08-05

    Applicant: University of Florida Research Foundation, Inc.

    Inventor： Prabhat Kumar Mishra ,  Aruna Jayasena Ranhotige

    IPC: G06F21/57 ,  G06F21/71

    Abstract: The present disclosure presents systems and methods for test pattern generation to detect a hardware Trojan. One such method comprises simulating an integrated circuit design; during the simulation, identifying rare nodes within the integrated circuit design that are activated less than a predefined rareness threshold, wherein the rare nodes include both signals and branches of the integrated circuit design; mapping each rare node to a stuck-at fault model; obtaining a first set of N test vectors for each stuck-at fault model using Automated Test Pattern Generation, wherein each of the N test vectors activates a same rare node of the integrated circuit design; identifying maximal cliques of rare nodes in the integrated circuit design that can be activated at a same time; and/or generating a second set of test vectors to activate each of the identified maximal cliques using Automated Test pattern Generation.

    Real-time detection and localization of DoS attacks in NoC based SoC architectures
    17.
    发明授权
    Real-time detection and localization of DoS attacks in NoC based SoC architectures 有权

    公开(公告)号：US11797667B2

    公开(公告)日：2023-10-24

    申请号：US16913850

    申请日：2020-06-26

    Applicant: University of Florida Research Foundation, Inc.

    Inventor： Prabhat Kumar Mishra ,  Thelijjagoda S N Charles ,  Yangdi Lyu

    IPC: G06F21/55

    CPC classification number: G06F21/552 ,  G06F2221/034

    Abstract: Various examples are provided related to software and hardware architectures that enable lightweight and real-time Denial-of-Service (DoS) and Distributed Denial-of-Service (DDoS) attack detection. In one example, among others, a method for detection and localization of denial-of-service (DoS) attacks includes detecting, by a router of an intellectual property (IP) core in a network-on-chip (NoC) based system-on-chip (SoC) architecture, a compromised packet stream based at least in part upon a packet arrival curve (PAC) associated with the router; identifying, by the IP core, a candidate IP core in the NoC as a potential attacker based at least in part upon a destination packet latency curve (DLC) associated with the IP core; and transmitting, by the router, a notification message indicating that the candidate IP core is the potential attacker to a router of the candidate IP core.

    LIGHTWEIGHT ENCRYPTION AND ANONYMOUS ROUTING IN NoC BASED SoCs
    19.
    发明申请
    LIGHTWEIGHT ENCRYPTION AND ANONYMOUS ROUTING IN NoC BASED SoCs 有权

    公开(公告)号：US20210034790A1

    公开(公告)日：2021-02-04

    申请号：US16937882

    申请日：2020-07-24

    Applicant: University of Florida Research Foundation, Inc.

    Inventor： Thelijjagoda S N Charles ,  Prabhat Kumar Mishra

    IPC: G06F21/75 ,  H04L9/30

    Abstract: Various examples are provided related to software and hardware architectures that enable lightweight encryption and anonymous routing in a network-on-chip (NoC) based system-on-chip (SoC). In one example, among others, method for lightweight encryption and anonymous routing includes identifying, by a source node in a network-on-chip (NoC) based system-on-chip (SoC) architecture, a routing path from the source node to a destination node in the NoC-based SoC architecture, where the routing path comprises the source node, a plurality of intermediate nodes in the NoC-based SoC architecture, and the destination node; generating, by the source node, a plurality of tuples, a number of tuples in the plurality of tuples being based on a threshold; and distributing, by the source node, the plurality of tuples to the plurality of intermediate nodes and the destination node.

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