公开(公告)号：US20190227934A1

公开(公告)日：2019-07-25

申请号：US15878062

申请日：2018-01-23

Applicant: VMware, Inc.

Inventor： Ye LI ,  Cyprien LAPLACE ,  Andrei WARKENTIN ,  Alexander FAINKICHEN ,  Regis DUCHESNE

IPC: G06F12/0815 ,  G06F12/0808

Abstract: An example method of maintaining cache coherency in a virtualized computing system includes: trapping access to a memory page by guest software in a virtual machine at a hypervisor managing the virtual machine, where the memory page is not mapped in a second stage page table managed by the hypervisor; performing cache coherency maintenance for instruction and data caches of a central processing unit (CPU) in the virtualized computing system in response to the trap; mapping the memory page in the second stage page table with execute permission; and resuming execution of the virtual machine.

公开(公告)号：US20190065213A1

公开(公告)日：2019-02-28

申请号：US15880964

申请日：2018-01-26

Applicant: VMware, Inc.

Inventor： Ye LI ,  Cyprien LAPLACE ,  Andrei WARKENTIN ,  Alexander FAINKICHEN ,  Regis DUCHESNE

IPC: G06F9/4401 ,  G06F17/30 ,  G06F9/455

Abstract: An example method of provisioning a virtual appliance to a virtualized computing system, comprising: deploying the virtual appliance to the virtualized computing system, the virtual appliance including a system partition, one or more disk images, and configuration data, the configuration data defining a virtual machine executable on each of a plurality of processor architectures, the system partition configured to boot on any one of the plurality of processor architectures; and booting the virtual appliance from the system partition.

公开(公告)号：US20180357070A1

公开(公告)日：2018-12-13

申请号：US15618010

申请日：2017-06-08

Applicant: VMware, Inc.

Inventor： Andrei WARKENTIN ,  Timothy P. MANN ,  Alexander FAINKICHEN

IPC: G06F9/44 ,  G06F12/109 ,  G06F11/22 ,  G06F11/27 ,  G06F9/455

CPC classification number: G06F9/4406 ,  G06F9/45558 ,  G06F11/2284 ,  G06F11/27 ,  G06F12/109 ,  G06F2009/45583 ,  G06F2212/657

Abstract: A method of re-mapping memory regions for firmware run-time services to a virtual address space of a kernel executed on a processor, includes the steps of selecting a re-mapping policy for re-mapping the memory regions for the firmware run-time services, creating a new mapping according to the selected re-mapping policy, and making a call to an application programming interface exposed by the firmware to apply the new map and re-map the memory regions for the firmware to the virtual address space of the kernel.

公开(公告)号：US20170364365A1

公开(公告)日：2017-12-21

申请号：US15183192

申请日：2016-06-15

Applicant: VMware, Inc.

Inventor： Andrei WARKENTIN ,  Harvey TUCH ,  Cyprien LAPLACE ,  Alexander FAINKICHEN

IPC: G06F9/44

Abstract: An example method of initializing a plurality of processors in a hardware platform of computing device for use by system software executing on the hardware platform includes: parsing a descriptor table that has been loaded into memory from firmware to identify an original boot protocol for initializing at least one secondary processor of the plurality of processors; creating at least one mailbox structure in the memory associated with the at least one secondary processor; causing the at least one secondary processor to execute secondary processor initialization code stored in the memory, the secondary processor initialization code implementing a mailbox-based boot protocol that uses the at least one mailbox structure to initialize the at least one secondary processor; and modifying the descriptor table to identify the mailbox-based boot protocol for initializing the at least one secondary processor in place of the original boot protocol.

公开(公告)号：US20230195487A1

公开(公告)日：2023-06-22

申请号：US17559313

申请日：2021-12-22

Applicant: VMware, Inc.

Inventor： Regis DUCHESNE ,  Andrei WARKENTIN ,  Cyprien LAPLACE ,  Ye LI ,  Shruthi Muralidhara HIRIYURU ,  Alexander FAINKICHEN ,  Sunil Kumar KOTIAN

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F2009/45583

Abstract: An example method of virtualizing a host virtual counter and timer in a central processing unit (CPU) of a virtualized host computer includes: creating, by a hypervisor of the host computer in response to power on of a virtual machine (VM), a guest virtual counter, the guest virtual counter comprising a data structure including scaling factors; mapping a shared memory page having the data structure into an address space of memory allocated to the VM; and notifying a guest operating system (OS) of the VM of a location in the address space for the shared memory page having the data structure, the guest OS being paravirtualized to scale the host virtual counter and timer based on the scaling factors of the guest virtual counter.

公开(公告)号：US20230195470A1

公开(公告)日：2023-06-22

申请号：US17559346

申请日：2021-12-22

Applicant: VMware, Inc.

Inventor： Cyprien LAPLACE ,  Sunil Kumar KOTIAN ,  Andrei WARKENTIN ,  Regis DUCHESNE ,  Alexander FAINKICHEN ,  Shruthi Muralidhara HIRIYURU ,  Ye LI

IPC: G06F9/38 ,  G06F9/455

CPC classification number: G06F9/3861 ,  G06F9/45558

Abstract: An example method of exception handling in a computer system is described. The computer system includes a physical central processing unit (PCPU) and a system memory, the system memory storing a first stack, a second stack, and a double fault stack associated with the PCPU. The method includes: storing, by an exception handler executing in the computer system, an exception frame on the double fault stack in response to a stack overflow condition of the first stack; switching, by the exception handler, a first stack pointer of the PCPU from pointing to the first stack to pointing to the double fault stack; setting a current stack pointer of the PCPU to the first stack pointer; and executing software on the PCPU with the current stack pointer pointing to the double fault stack.

公开(公告)号：US20210224090A1

公开(公告)日：2021-07-22

申请号：US16744356

申请日：2020-01-16

Applicant: VMware, Inc.

Inventor： Andrei WARKENTIN ,  Cyprien LAPLACE ,  Regis DUCHESNE ,  Alexander FAINKICHEN ,  Shruthi Muralidhara HIRIYURU ,  Ye LI

IPC: G06F9/455

Abstract: An example method of interfacing with a hypervisor in a computing system is described, which includes a processor having at least three hierarchical privilege levels including a third privilege level more privileged than a second privilege level, the second privilege level more privileged than a first privilege level. The method includes: identifying an input/output (I/O) space instruction, not supported by the processor, to be performed for backdoor communication between the hypervisor and guest software executing in a virtual machine (VM) managed by the hypervisor, the hypervisor executing at the third privilege level; writing one or more parameters to one or more registers of the processor that are mapped to one or more unsupported registers used by the I/O space instruction; writing a value indicative of the I/O space instruction to a designated register of the processor; executing an instruction, by the guest software executing at the first or second privilege level, which is trapped to the third privilege level.

公开(公告)号：US20190391814A1

公开(公告)日：2019-12-26

申请号：US16013263

申请日：2018-06-20

Applicant: VMware, Inc.

Inventor： Andrei WARKENTIN ,  Cyprien LAPLACE ,  Alexander FAINKICHEN ,  Ye LI ,  Regis DUCHESNE

IPC: G06F9/38 ,  G06F9/455 ,  G06F12/10

Abstract: An example method of implementing firmware runtime services in a computer system having a processor with a plurality of hierarchical privilege levels, the method including: calling, from software executing at a first privilege level of the processor, a runtime service stub in a firmware of the computer system; executing, by the runtime service stub, an upcall instruction from the first privilege level to a second privilege level of the processor that is more privileged than the first privilege level; and executing, by a handler, a runtime service at the second privilege level in response to execution of the upcall instruction.

公开(公告)号：US20190213095A1

公开(公告)日：2019-07-11

申请号：US15865770

申请日：2018-01-09

Applicant: VMware, Inc.

Inventor： Andrei WARKENTIN ,  Cyprien LAPLACE ,  Regis DUCHESNE ,  Ye LI ,  Alexander FAINKICHEN

IPC: G06F11/30 ,  G06F13/10 ,  G06F9/455

Abstract: A method of detecting virtualization in a computing system, which includes a processor having at least three hierarchical privilege levels including a third privilege level more privileged than a second privilege level, the second privilege level more privileged than a first privilege level, is described. The method includes: executing a program on the processor at a privilege level less privileged than the third privilege level, the program including a load-exclusive instruction of the processor, followed by at least one instruction of the processor capable of being trapped to the third privilege level, followed by a store-exclusive instruction of the processor; and determining presence or absence of virtualization software at least a portion of which executes at the third privilege level in response to a return status of the store-exclusive instruction.

公开(公告)号：US20190026232A1

公开(公告)日：2019-01-24

申请号：US15655182

申请日：2017-07-20

Applicant: VMware, Inc.

Inventor： Andrei WARKENTIN ,  Alexander FAINKICHEN ,  Cyprien LAPLACE ,  Ye LI ,  Regis DUCHESNE

IPC: G06F12/1036 ,  H04L12/801 ,  H04L12/755 ,  H04L12/24

Abstract: An example method of scanning a guest virtual address (GVA) space generated by a guest operating system executing in a virtual machine of a virtualized computing system includes setting, in a scan of the GVA space by a hypervisor that manages the virtual machine, a current GVA to a first GVA in the GVA space; executing, on a processor allocated to the virtual machine, an address translation instruction, which is in an instruction set of the processor, to perform a first address translation of the current GVA; reading a register of the processor to determine a first error resulting from the first address translation; determining, in response to the first error, a level of a faulting page table in a first page table hierarchy generated by the guest operating system; and setting the current GVA to a second GVA based on the level of the faulting page table.