公开(公告)号：US20210026648A1

公开(公告)日：2021-01-28

申请号：US16521434

申请日：2019-07-24

Applicant: VMware, Inc.

Inventor： Andrei WARKENTIN ,  Cyprien LAPLACE ,  Ye LI ,  Alexander FAINKICHEN ,  Regis DUCHESNE

IPC: G06F9/4401 ,  G06F16/22

Abstract: A method for generating boot tables for a device having access to device information. It is determined whether there exists at least one system boot table stored in a memory. If it is determined that a system boot table does not exist, the device information is retrieved, and the device information is converted to at least one boot table. The converting includes generating a first boot table by populating the first boot table with information of components of the device that have a correspondence to a computer system boot information standard. The generating also includes generating a second boot table for another component of the device that does not have a correspondence to the computer system boot information standard, by creating an entry in the second boot table that is populated with an identifier used to find a compatible component defined in the computer system boot standard.

公开(公告)号：US20190258590A1

公开(公告)日：2019-08-22

申请号：US15898714

申请日：2018-02-19

Applicant: VMware, Inc.

Inventor： Andrei WARKENTIN ,  Cyprien LAPLACE ,  Ye LI ,  Alexander FAINKICHEN ,  Regis DUCHESNE

IPC: G06F13/10 ,  G06F9/455

Abstract: An example method of accessing a computing system includes: providing serial terminal driver configured to interface a serial port in a hardware platform of the computer system; providing a console object configured to communicate with an operating system (OS) in a software platform of the computer system and the serial terminal driver; connecting to the console object through the serial port via a computer terminal; sending text and commands from the console object to the computer terminal; and rendering, by the computer terminal, a console for presentation on a display of the computer terminal.

公开(公告)号：US20190012179A1

公开(公告)日：2019-01-10

申请号：US15644670

申请日：2017-07-07

Applicant: VMware, Inc.

Inventor： Andrei WARKENTIN ,  Cyprien LAPLACE ,  Regis DUCHESNE ,  Alexander FAINKICHEN ,  Ye LI

IPC: G06F9/44 ,  G06F3/06 ,  G06F12/1009 ,  G06F9/38 ,  G06F12/121 ,  G06F12/1027

CPC classification number: G06F9/4403 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/068 ,  G06F9/38 ,  G06F9/4405 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/121 ,  G06F2212/65 ,  G06F2212/68

Abstract: A method of initializing a secondary processor pursuant to a soft reboot of system software comprises storing code to be executed by the secondary processor in memory, building first page tables to map the code into a first address space and second page tables to identically map the code into a second address space, fetching a first instruction of the code based on a first virtual address in the first address space and the first page tables, and executing the code beginning with the first instruction to switch from the first to the second page tables. The method further comprises, fetching a next instruction of the code using a second virtual address, which is identically mapped to a corresponding machine address, turning off a memory management unit of the secondary processor, and executing a waiting loop until a predetermined location in the physical memory changes in value.

公开(公告)号：US20210224089A1

公开(公告)日：2021-07-22

申请号：US16744351

申请日：2020-01-16

Applicant: VMware, Inc.

Inventor： Cyprien LAPLACE ,  Regis DUCHESNE ,  Andrei WARKENTIN ,  Ye LI ,  Alexander FAINKICHEN

IPC: G06F9/455

Abstract: An example method of interfacing with a hypervisor in a computing system is described. The computing system includes a processor having at least three hierarchical privilege levels including a third privilege level more privileged than a second privilege level, the second privilege level more privileged than a first privilege level. The method includes configuring, by the hypervisor executing at the third privilege level, the processor to trap reads to a debug communication channel (DCC) status register of the processor to the third privilege level; trapping, at the hypervisor, a read to the DCC status register by guest software executing in a virtual machine (VM) managed by the hypervisor, the guest software executing at the first or second privilege level; reading, at the hypervisor, a plurality of registers of the processor to obtain data stored by the guest software; and returning execution from the hypervisor to the guest software.

公开(公告)号：US20210133315A1

公开(公告)日：2021-05-06

申请号：US16671106

申请日：2019-10-31

Applicant: VMware, Inc.

Inventor： Ye LI ,  David OTT ,  Cyprien LAPLACE ,  Andrei WARKENTIN ,  Regis DUCHESNE

IPC: G06F21/53 ,  G06F9/455 ,  G06F21/60

Abstract: System and method for creating and managing trusted execution environments (TEEs) using different underlying hardware TEE mechanisms use a virtual secure enclave device which runs in a virtualized environment in a computer system. The device enables an enclave command transmitted to the virtual secure enclave device to be retrieved and parsed to extract an enclave operation to be executed. A TEE backend module is used to interact with a particular hardware TEE mechanism among those available in the computer system. The module ensures the enclave operation for the software process is executed by the particular hardware TEE mechanism, or the TEE scheme based on a particular hardware TEE mechanism.

公开(公告)号：US20230195484A1

公开(公告)日：2023-06-22

申请号：US17553607

申请日：2021-12-16

Applicant: VMware, Inc.

Inventor： Andrei WARKENTIN ,  Ye LI ,  Alexander FAINKICHEN ,  Regis DUCHESNE ,  Cyprien LAPLACE ,  Shruthi Muralidhara HIRIYURU ,  Sunil Kumar KOTIAN

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F2009/45583

Abstract: An example method of managing guest time for a virtual machine (VM) supported by a hypervisor of a virtualized host computer includes: configuring, by the hypervisor, a central processing unit (CPU) of the host computer to trap, to the hypervisor, access by guest code in the VM to a physical counter and timer of the CPU; configuring, by the hypervisor, the guest code in the VM to use the physical counter and timer of the CPU rather than a virtual counter and timer of the CPU; trapping, at the hypervisor, an access to the physical counter and timer by the guest code; and executing, by the hypervisor, the access to the physical counter and timer on behalf of the guest code while compensating for an adjustment of a system count of the physical counter and timer to maintain the guest time as scaled with respect to frequency of the physical counter and timer.

公开(公告)号：US20190227934A1

公开(公告)日：2019-07-25

申请号：US15878062

申请日：2018-01-23

Applicant: VMware, Inc.

Inventor： Ye LI ,  Cyprien LAPLACE ,  Andrei WARKENTIN ,  Alexander FAINKICHEN ,  Regis DUCHESNE

IPC: G06F12/0815 ,  G06F12/0808

Abstract: An example method of maintaining cache coherency in a virtualized computing system includes: trapping access to a memory page by guest software in a virtual machine at a hypervisor managing the virtual machine, where the memory page is not mapped in a second stage page table managed by the hypervisor; performing cache coherency maintenance for instruction and data caches of a central processing unit (CPU) in the virtualized computing system in response to the trap; mapping the memory page in the second stage page table with execute permission; and resuming execution of the virtual machine.

公开(公告)号：US20190065213A1

公开(公告)日：2019-02-28

申请号：US15880964

申请日：2018-01-26

Applicant: VMware, Inc.

Inventor： Ye LI ,  Cyprien LAPLACE ,  Andrei WARKENTIN ,  Alexander FAINKICHEN ,  Regis DUCHESNE

IPC: G06F9/4401 ,  G06F17/30 ,  G06F9/455

Abstract: An example method of provisioning a virtual appliance to a virtualized computing system, comprising: deploying the virtual appliance to the virtualized computing system, the virtual appliance including a system partition, one or more disk images, and configuration data, the configuration data defining a virtual machine executable on each of a plurality of processor architectures, the system partition configured to boot on any one of the plurality of processor architectures; and booting the virtual appliance from the system partition.

公开(公告)号：US20230195487A1

公开(公告)日：2023-06-22

申请号：US17559313

申请日：2021-12-22

Applicant: VMware, Inc.

Inventor： Regis DUCHESNE ,  Andrei WARKENTIN ,  Cyprien LAPLACE ,  Ye LI ,  Shruthi Muralidhara HIRIYURU ,  Alexander FAINKICHEN ,  Sunil Kumar KOTIAN

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F2009/45583

Abstract: An example method of virtualizing a host virtual counter and timer in a central processing unit (CPU) of a virtualized host computer includes: creating, by a hypervisor of the host computer in response to power on of a virtual machine (VM), a guest virtual counter, the guest virtual counter comprising a data structure including scaling factors; mapping a shared memory page having the data structure into an address space of memory allocated to the VM; and notifying a guest operating system (OS) of the VM of a location in the address space for the shared memory page having the data structure, the guest OS being paravirtualized to scale the host virtual counter and timer based on the scaling factors of the guest virtual counter.

公开(公告)号：US20230195470A1

公开(公告)日：2023-06-22

申请号：US17559346

申请日：2021-12-22

Applicant: VMware, Inc.

Inventor： Cyprien LAPLACE ,  Sunil Kumar KOTIAN ,  Andrei WARKENTIN ,  Regis DUCHESNE ,  Alexander FAINKICHEN ,  Shruthi Muralidhara HIRIYURU ,  Ye LI

IPC: G06F9/38 ,  G06F9/455

CPC classification number: G06F9/3861 ,  G06F9/45558

Abstract: An example method of exception handling in a computer system is described. The computer system includes a physical central processing unit (PCPU) and a system memory, the system memory storing a first stack, a second stack, and a double fault stack associated with the PCPU. The method includes: storing, by an exception handler executing in the computer system, an exception frame on the double fault stack in response to a stack overflow condition of the first stack; switching, by the exception handler, a first stack pointer of the PCPU from pointing to the first stack to pointing to the double fault stack; setting a current stack pointer of the PCPU to the first stack pointer; and executing software on the PCPU with the current stack pointer pointing to the double fault stack.