公开(公告)号：US4300194A

公开(公告)日：1981-11-10

申请号：US8004

申请日：1979-01-31

申请人： John J. Bradley ,  Ming T. Miu ,  Jian-Kuo Shen

发明人： John J. Bradley ,  Ming T. Miu ,  Jian-Kuo Shen

IPC分类号： G06F13/36 ,  G06F13/362 ,  G06F3/04

CPC分类号： G06F13/362

摘要： Multiple common buses are provided for coupling a plurality of units in a data processing system for the transfer of information therebetween. The central processing unit (CPU) allocates the multiple common buses to one of the units in response to bus requests received from various units desiring to use the common buses. Bus requests are generated in a synchronous manner by use of a timing signal originating in the CPU which is connected in series between the one or more units on each of the multiple common buses.

摘要翻译： 提供多个公共总线用于在数据处理系统中耦合多个单元以便在其间传送信息。 中央处理单元（CPU）响应于从希望使用公共总线的各个单元接收的总线请求，将多个公共总线分配给单元之一。 通过使用源自CPU的定时信号以同步方式产生总线请求，该定时信号串联连接在多个公共总线中的每一个上的一个或多个单元之间。

公开(公告)号：US4293908A

公开(公告)日：1981-10-06

申请号：US8001

申请日：1979-01-31

申请人： John J. Bradley ,  Thomas O. Holtey ,  Robert C. Miller ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

发明人： John J. Bradley ,  Thomas O. Holtey ,  Robert C. Miller ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

IPC分类号： G06F13/28 ,  G06F13/362 ,  G06F13/00

CPC分类号： G06F13/362 ,  G06F13/282

摘要： In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processing unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Direct Memory Access (DMA) data transfer operation in which the requesting IOC requests a DMA data transfer of the CPU. Means are provided within the system for: resolving conflicting requests for the one or more common buses, the CPU to acknowledge the DMA request, the IOC to transfer the address of the location where the unit of data is to be written into main memory followed by the unit of data, or the IOC to transfer the address of the location in main memory from which the unit of data is to be read and then receive the unit of data read from main memory.

摘要翻译： 在包括一个或多个公共总线的数据处理系统中，多个输入/输出控制器连接到该公共总线用于传送数据，数据块可以在主存储器和与操作同步的输入/输出控制器（IOC）之间传送 的中央处理单元（CPU）。 提供逻辑用于在直接存储器访问（DMA）数据传输操作期间传送一个数据单元，其中请求IOC请求CPU的DMA数据传输。 在系统内提供的装置是：解决对一个或多个公共总线的冲突请求，CPU确认DMA请求，IOC将要写入数据单元的位置的地址传送到主存储器，之后是 数据单元或IOC传输要从其读取数据单元的主存储器中的位置的地址，然后接收从主存储器读取的数据单元。

公开(公告)号：US4785398A

公开(公告)日：1988-11-15

申请号：US811044

申请日：1985-12-19

申请人： Thomas F. Joyce ,  Ming T. Miu ,  Jian-Kuo Shen ,  Forrest M. Phillips

发明人： Thomas F. Joyce ,  Ming T. Miu ,  Jian-Kuo Shen ,  Forrest M. Phillips

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F13/00

CPC分类号： G06F12/0882 ,  G06F12/0831 ,  G06F12/1063

摘要： A multiprocessor computer system includes a main memory and a plurality of central processing units (CPU's) which are connected to share main memory via a common bus network. Each CPU has instruction and data cache units, each organized on a page basis for complete operating compatibility with user processes. Each cache unit includes a number of content addressable memories (CAM's) and directly addressable memories (RAM's) organized to combine associative and direct mapping of data or instructions on a page basis. An input CAM in response to a CPU address provides a cache address which includes a page level number for identifying where all of the required information resides in the other memories for processing requests relating to the page. This organization permits the processing of either virtual or physical addresses with improved speed and reduced complexity and the ability to detect and eliminate both consistency and synonym problems.

摘要翻译： 多处理器计算机系统包括主存储器和多个中央处理单元（CPU），其经由公共总线网络连接以共享主存储器。 每个CPU都有指令和数据缓存单元，每个单元都以页面为单位进行组织，以便与用户进程完全兼容。 每个高速缓存单元包括多个内容可寻址存储器（CAM）和可直接寻址的存储器（RAM），其被组织以组合以组合基于页面的数据或指令的关联和直接映射。 响应于CPU地址的输入CAM提供缓存地址，该缓存地址包括用于识别所有所需信息驻留在其他存储器中的页面级别号码，用于处理与该页面有关的请求。 该组织允许以改进的速度和降低的复杂性处理虚拟或物理地址，并且能够检测和消除一致性和同义词问题。

公开(公告)号：US4459665A

公开(公告)日：1984-07-10

申请号：US008123

申请日：1979-01-31

申请人： Ming T. Miu ,  John J. Bradley ,  Jian-Kuo Shen

发明人： Ming T. Miu ,  John J. Bradley ,  Jian-Kuo Shen

IPC分类号： G06F3/06 ,  G06F13/362 ,  G06F13/00

CPC分类号： G06F13/362

摘要： One or more common buses are provided for coupling a plurality of units in a data processing system for transfer of information therebetween. The central processing unit (CPU) allocates the one or more common buses to one of the requesting units as a function of request type and on which of one or more common buses the requesting unit is located. Bus requests are generated in a synchronous manner by use of a timing signal originating in the CPU which is connected in series between the one or more units on each of the one or more common buses.

摘要翻译： 一个或多个公共总线被提供用于耦合数据处理系统中的多个单元以在其间传送信息。 中央处理单元（CPU）根据请求类型和请求单元所位于的一个或多个公共总线中的哪一个将请求单元之一分配给一个或多个公共总线。 通过使用源自CPU的定时信号以同步方式产生总线请求，该定时信号串联连接在一个或多个公共总线中的每一个上的一个或多个单元之间。

公开(公告)号：US4383295A

公开(公告)日：1983-05-10

申请号：US11001

申请日：1979-02-09

申请人： Robert C. Miller ,  John J. Bradley ,  Boyd E. Darden ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

发明人： Robert C. Miller ,  John J. Bradley ,  Boyd E. Darden ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

IPC分类号： G06F3/02 ,  G06F9/06

CPC分类号： G06F3/0227

摘要： In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processor unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and later provides the CPU with a channel number assigned to the requesting IOC. In order to allow a data entry operator inputting data via a peripheral device connected to an IOC the ability to correct errors, a backspace character is provided so that the operator can enter it to indicate to the system to ignore the preceding character. Logic is provided within the system to allow a DMC IOC to detect the output of a backspace character from the peripheral device connected to the IOC and to inform the CPU of the entry of the backspace character by a special (backspace) input/output interrupt. Further logic is provided within the CPU to adjust pointers to the main memory input buffer to effectively ignore the byte of data corresponding to the character preceding the backspace character. Still further logic is provided within the DMC IOC to prohibit the sending of special (backspace) input/output interrupts to the CPU if there are no bytes of data remaining in the input buffer.

摘要翻译： 在包括一个或多个公共总线的数据处理系统中，多个输入/输出控制器连接到该公共总线用于传送数据，数据块可以在主存储器和与操作同步的输入/输出控制器（IOC）之间传送 的中央处理器单元（CPU）。 提供逻辑用于在数据复用控制（DMC）数据传输操作期间传输一个数据单元，其中请求的IOC请求CPU的DMC数据传输，并且稍后向CPU提供分配给请求的IOC的通道号 。 为了允许数据输入操作者通过连接到IOC的外围设备输入数据以校正错误的能力，提供退格字符，以便操作者可以进入它以指示系统忽略前一个字符。 在系统中提供逻辑，以允许DMC IOC从连接到IOC的外围设备检测退格字符的输出，并通过特殊（退格）输入/输出中断向CPU通知退格字符的输入。 在CPU内提供进一步的逻辑来调整指向主存储器输入缓冲器的指针，以有效地忽略与退格字符之前的字符相对应的数据字节。 在DMC IOC中还提供了一些逻辑，以禁止在CPU中输入/输出特殊的（空格）输入/输出中断，如果输入缓冲区中没有字节数据。

公开(公告)号：US4300193A

公开(公告)日：1981-11-10

申请号：US8003

申请日：1979-01-31

申请人： John J. Bradley ,  Robert C. Miller ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

发明人： John J. Bradley ,  Robert C. Miller ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

IPC分类号： G06F13/28 ,  G06F3/00

CPC分类号： G06F13/282

摘要： In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of information, blocks of information may be transferred between main memory and an input/output controller (IOC) synchronously with operations of the central processor unit (CPU). Logic is provided for enabling one unit of the block of information to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and provides the CPU with a channel number assigned to the requesting IOC. Means are provided within the CPU for determining: the direction of the data transfer, the address of the location of the unit of data to be transferred to/from the main memory, and the number of units of data remaining to be transferred between the main memory and the IOC.

摘要翻译： 在包括一个或多个公共总线的数据处理系统中，多个输入/输出控制器连接到多个输入/输出控制器用于信息的传送，信息块可以在主存储器和与操作同步的输入/输出控制器（IOC）之间传送 的中央处理器单元（CPU）。 逻辑被提供用于使得在数据复用控制（DMC）数据传送操作期间传送信息块的一个单元，其中请求的IOC请求CPU的DMC数据传送，并向CPU提供分配给 请求IOC。 在CPU内提供用于确定：数据传送的方向，要传送到主存储器的数据单元的位置的地址以及在主存储器之间传输的剩余数据的单元数量 记忆和国际奥委会。

公开(公告)号：US4495571A

公开(公告)日：1985-01-22

申请号：US339278

申请日：1982-01-15

申请人： Theodore R. Staplin, Jr. ,  John J. Bradley ,  Richard L. King ,  Robert C. Miller ,  Ming T. Miu ,  Jian-Kuo Shen

发明人： Theodore R. Staplin, Jr. ,  John J. Bradley ,  Richard L. King ,  Robert C. Miller ,  Ming T. Miu ,  Jian-Kuo Shen

IPC分类号： G06F13/12 ,  G06F13/362 ,  G06F3/04 ,  G06F13/00

CPC分类号： G06F13/122 ,  G06F13/362

摘要： A data processing system which includes a central processing unit coupled over a common bus with a plurality of input/output controllers (IOCs) and main memory includes apparatus which allows an IOC to signal the CPU to wait and retry the current I/O instruction. Other apparatus is provided which enables the CPU to continually retry the I/O instruction until the IOC accepts or rejects the I/O instruction and which further allows the CPU to suspend the retrying of the I/O instruction and to process interrupt requests and data transfer requests from any one of the plurality of IOCs. After processing the interrupt or data transfer request, system control is returned to retrying the I/O instruction.

摘要翻译： 包括通过公共总线与多个输入/输出控制器（IOC）和主存储器耦合的中央处理单元的数据处理系统包括允许IOC发信号通知CPU等待并重试当前I / O指令的装置。 提供了其他设备，使得CPU能够连续地重试I / O指令，直到IOC接受或拒绝I / O指令，并且还允许CPU暂停重试I / O指令并处理中断请求和数据 转移来自多个IOC中的任何一个的请求。 处理中断或数据传输请求后，返回系统控制以重试I / O指令。

公开(公告)号：US4292668A

公开(公告)日：1981-09-29

申请号：US8002

申请日：1979-01-31

申请人： Robert C. Miller ,  John J. Bradley ,  Richard L. King ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

发明人： Robert C. Miller ,  John J. Bradley ,  Richard L. King ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

IPC分类号： G06F13/28 ,  G06F13/362 ,  G06F3/00

CPC分类号： G06F13/362 ,  G06F13/285

摘要： In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processor unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and later provides the CPU with a channel number assigned to the requesting IOC. Means are provided within the system for: resolvng conflicting requests for the one or more common buses, the CPU to acknowledge the DMC request, identifying the requesting IOC to the CPU, accessing one unit of data from main memory or the IOC, and transferring the unit of data to the IOC or main memory.

摘要翻译： 在包括一个或多个公共总线的数据处理系统中，多个输入/输出控制器连接到该公共总线用于传送数据，数据块可以在主存储器和与操作同步的输入/输出控制器（IOC）之间传送 的中央处理器单元（CPU）。 提供逻辑用于在数据复用控制（DMC）数据传输操作期间传输一个数据单元，其中请求的IOC请求CPU的DMC数据传输，并且稍后向CPU提供分配给请求的IOC的通道号 。 在系统内提供了：解决对一个或多个公共总线的冲突请求，CPU确认DMC请求，识别请求的IOC到CPU，从主存储器或IOC访问一个单元的数据，并传送 数据单位到IOC或主存储器。

公开(公告)号：US4783735A

公开(公告)日：1988-11-08

申请号：US810945

申请日：1985-12-19

申请人： Ming T. Miu ,  Thomas F. Joyce ,  Jian-Kuo Shen ,  Forrest M. Phillips

发明人： Ming T. Miu ,  Thomas F. Joyce ,  Jian-Kuo Shen ,  Forrest M. Phillips

IPC分类号： G06F12/12 ,  G06F12/02

CPC分类号： G06F12/123

摘要： A least recently used replacement level generator is constructed to include n number of register stages connected in tandem. A comparison circuit associated with each stage except the last stage compare the contents of that stage with an input level value which is to be loaded into the input stage. In the absence of an identical comparison, each stage generates a shift enable signal which is passed on to the next succeeding stage. An identical comparison inhibits the generation of the shift enable signal. Therefore, when a clock signal is applied to the device, register stages, in the presence of a control signal, cause the input level to be loaded into the input stage while the level contents of the register stages are simultaneously shifted through successive stages including the register stage whose contents are identical to the input level under the control of the shift enable signal. The contents of the output register stage accurately and instantaneously defines the least recently used replacement level for use by a cache memory.

摘要翻译： 构造最少最近使用的替换电平发生器以包括串联连接的n个寄存器级。 与除最后阶段之外的每个阶段相关联的比较电路将该级的内容与要加载到输入级的输入电平值进行比较。 在没有相同的比较的情况下，每个级产生一个传递到下一个后级的移位使能信号。 相同的比较抑制了移位使能信号的产生。 因此，当时钟信号被施加到器件时，在存在控制信号的情况下，寄存器级使得输入电平被加载到输入级，同时寄存器级的电平内容同时被移位到包括 其寄存器级的内容与在移位使能信号的控制下的输入电平相同。 输出寄存器级的内容准确和瞬时地定义了由缓存存储器使用的最近最少使用的替换级别。

公开(公告)号：US4484271A

公开(公告)日：1984-11-20

申请号：US392500

申请日：1982-06-28

申请人： Ming T. Miu ,  John J. Bradley ,  Jian-Kuo Shen

发明人： Ming T. Miu ,  John J. Bradley ,  Jian-Kuo Shen

IPC分类号： G06F9/26

CPC分类号： G06F9/268

摘要： A hardware interrupt apparatus for assigning the microprogrammed control system to the highest priority hardware interrupt requesting service. In a microprogrammed control system having at least one hardware interrupt, the presence of a hardware interrupt request will cause the interruption of the currently executing microprogram at the end of the current microinstruction. The address of the next microinstruction in the interrupted microprogram is saved in a hardware interrupt return address register and the next microinstruction address is generated as a function of the particular hardware interrupt to be serviced. A microprogram dedicated to servicing the particular hardware interrupt is then entered at the hardware interrupt generated next microinstruction address. Logic is provided within each microinstruction to inhibit hardware interrupts. Logic is provided within each microinstruction to indicate that the address of the next microinstruction should be taken from the hardware interrupt return address register, thereby allowing for the resumption of the interrupted microprogram. The hardware interrupt apparatus is further organized such that the entry to a second hardware interrupt service microprogram can be made upon the completion of a first hardware interrupt service microprogram without having to return to the original microprogram interrupted by the first hardware interrupt. Upon completion of the second hardware interrupt microprogram service routine, return can be made to the original microprogram interrupted by the first hardware interrupt.

摘要翻译： 一种硬件中断装置，用于将微程序控制系统分配给最高优先级的硬件中断请求服务。 在具有至少一个硬件中断的微程序控制系统中，存在硬件中断请求将导致在当前微指令结束时当前执行的微程序的中断。 中断微程序中的下一个微指令的地址被保存在硬件中断返回地址寄存器中，并且根据要维护的特定硬件中断产生下一个微指令地址。 然后在产生下一个微指令地址的硬件中断输入专用于维护特定硬件中断的微程序。 在每个微指令内提供逻辑以禁止硬件中断。 在每个微指令内提供逻辑，以指示下一个微指令的地址应从硬件中断返回地址寄存器中取出，从而允许恢复中断的微程序。 硬件中断装置被进一步组织，使得可以在完成第一硬件中断服务微程序之后进入到第二硬件中断服务微程序，而不必返回到由第一硬件中断中断的原始微程序。 在完成第二个硬件中断微程序服务程序后，可以返回由第一个硬件中断中断的原始微程序。