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公开(公告)号：US5442704A
公开(公告)日：1995-08-15
申请号：US181691
申请日：1994-01-14
申请人： Thomas O. Holtey
发明人： Thomas O. Holtey
CPC分类号： G07F7/1008 , G06Q20/341 , G06Q20/3576
摘要： A secure memory card includes a microprocessor on a single semiconductor chip which interconnects through an internal bus to a number of non-volatile addressable memory chips. The microprocessor includes an addressable non-volatile memory for storing information including a number of key values and program instruction information. Each chip's memory is organized into a number of blocks, each block including a number of rows of byte locations. Each row of each block further includes a lock bit location, the total number of which provide storage for a lock value uniquely coded to utilize a predetermined characteristic of the memory to ensure data protection. Each memory chip is constructed to include security control logic circuits which include a security access control unit and a volatile access control memory containing a plurality of access control storage elements. Under the control of a predetermined set of instructions, the security access control unit performs a predetermined key validation operation by comparing key values against the bit contents of lock bit locations read out a bit at a time during an authentication procedure with a host computer. After the successful performance of the key validation procedure, the microprocessor sets one of the storage elements of the volatile access control memory for enabling user access to block data.
摘要翻译： 安全存储卡包括在单个半导体芯片上的微处理器，其通过内部总线与多个非易失性可寻址存储器芯片互连。 微处理器包括可寻址的非易失性存储器，用于存储包括多个键值和程序指令信息的信息。 每个芯片的存储器被组织成多个块，每个块包括多个字节位置行。 每个块的每一行还包括锁定位置，其总数为唯一编码的锁值提供存储以利用存储器的预定特性以确保数据保护。 每个存储器芯片被构造为包括安全控制逻辑电路，其包括安全访问控制单元和包含多个访问控制存储元件的易失性访问控制存储器。 在预定的一组指令的控制下，安全访问控制单元通过将密钥值与在主计算机的认证过程期间一次读出的锁定位位置的位内容进行比较来执行预定的密钥验证操作。 在成功执行密钥验证过程之后，微处理器设置易失性访问控制存储器的存储元件之一，以使用户能够访问块数据。
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公开(公告)号：US4945473A
公开(公告)日：1990-07-31
申请号：US051084
申请日：1987-05-15
摘要： A communications controller interface for emulating the previous system employing a plurality of line units in which data is transmitted and received. The interface includes a microprocessor-controlled interface control unit having an interface memory having a plurality of addressable storage locations. The interface memory is mapped by dividing it into a number of groups of locations corresponding to the number of communication lines with each group of locations being subdivided into further locations including a location for storage of receive data, a location for storage of transmit data, and a control location. There are a number of control elements each for generating a sequence of signals for different tasks to be performed by the interface control unit. These control elements are interconnected to the interface control unit and to the interface memory so that the multi-line communications unit is able to access different ones of the control locations for updating the status of the lines and further enabling the microprocessor-controlled interface control unit to transfer data to and from the transmit data and receive data locations of the lines in the predetermined sequence consistent with the status.
摘要翻译： 一种通信控制器接口，用于仿真先前系统，采用多个发送和接收数据的线路单元。 接口包括微处理器控制的接口控制单元，其具有具有多个可寻址存储位置的接口存储器。 通过将接口存储器划分成与通信线路数量相对应的多个位置组，将每组位置细分为另外的位置，包括用于存储接收数据的位置，用于存储发送数据的位置，以及 控制位置。 存在多个控制元件，用于生成用于由接口控制单元执行的不同任务的信号序列。 这些控制元件互连到接口控制单元和接口存储器，使得多线通信单元能够访问不同的控制位置以更新线路的状态，并且进一步启用微处理器控制的接口控制单元 将数据传输到发送数据和从发送数据传送数据，并以与状态一致的预定顺序接收线路的数据位置。
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公开(公告)号：US4633244A
公开(公告)日：1986-12-30
申请号：US537929
申请日：1983-09-30
CPC分类号： H01J29/48 , G09G1/20 , H01J2229/507
摘要： A high definition page display system for graphics and text utilizing multiple beams in a CRT is disclosed. Information for the several lines which are written simultaneously is made available in parallel. The invention is described in terms of a character set and text generation, but the same principles apply to any other graphic or bit map and to storage in ROMs or loadable RAMs. Each beam of a multiple CRT tube is biased to generate a portion of a character or graphic as it scans across the tube. It takes 12 lines to scan a character with a N-beam tube, 12 over N character scans are therefore required. With the same scanning speed as with a single beam, this factor can be used to increase definition (i.e. number of lines). Also the advantage of multiple beams can be used to reduce scanning speed, if this is useful to improve brightness or spot definition, or to increase the number of dots per line. Reduced scanning speed can also reduce costs, particularly if it brings the scan rate in line with standard components available commerically. Another way to use the advantages would be higher refresh rates.
摘要翻译： 公开了一种用于在CRT中使用多个光束的图形和文本的高清晰度页面显示系统。 同时写入的几条线的信息可以并行提供。 根据字符集和文本生成描述本发明，但是相同的原理适用于任何其他图形或位图，并且存储在ROM或可加载RAM中。 多个CRT管的每个光束被偏压以在其穿过管扫描时产生字符或图形的一部分。 需要12行扫描带有N光束管的字符，因此需要12个N字符扫描。 以与单个波束相同的扫描速度，该因子可用于增加定义（即线数）。 此外，如果这对于提高亮度或光斑定义有用，或者增加每行的点数，则可以使用多个光束的优点来降低扫描速度。 降低扫描速度也可以降低成本，特别是如果扫描速率符合标准组件可商用。 另一种使用优势的方法是更高的刷新率。
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4.发明授权Communications subsystem having a self-latching data monitor and storage device 失效通信子系统具有自锁数据监视器和存储设备
公开(公告)号：US4393461A
公开(公告)日：1983-07-12
申请号：US194311
申请日：1980-10-06
CPC分类号： G06F13/385
摘要： A communications subsystem having a microprocessor coupled to an address bus and a data bus includes a latching register also coupled to the address bus and the data bus. The latching register is responsive to signals from the data bus and address bus for storing bits representative of a direct connect mode, a clear to send mode, and a bit oriented or byte control protocol mode.
摘要翻译： 具有耦合到地址总线和数据总线的微处理器的通信子系统包括还耦合到地址总线和数据总线的锁存寄存器。 锁存寄存器响应来自数据总线和地址总线的信号，用于存储代表直接连接模式，清除发送模式和面向位或字节控制协议模式的位。
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公开(公告)号：US4157587A
公开(公告)日：1979-06-05
申请号：US863095
申请日：1977-12-22
申请人： Thomas F. Joyce , Thomas O. Holtey
发明人： Thomas F. Joyce , Thomas O. Holtey
CPC分类号： G06F12/123 , G06F12/0862 , F02B2075/027 , G06F2212/6022
摘要： A data processing system includes a plurality of system units all connected in common to a system bus. The system units include a central processor (CPU), a memory system and a high speed buffer or cache system. The cache system is word oriented and comprises a directory, a data buffer and associated control logic. The CPU requests data words by sending a main memory address of the requested data word to the cache system. If the cache does not have the information, apparatus in the cache requests the information from main memory, and in addition, the apparatus requests additional information from consecutively higher addresses. If main memory is busy, the cache has apparatus to request fewer words.
摘要翻译： 数据处理系统包括多个系统单元，它们都共同连接到系统总线。 系统单元包括中央处理器（CPU），存储器系统和高速缓冲器或缓存系统。 缓存系统是面向字的，包括一个目录，一个数据缓冲器和相关的控制逻辑。 CPU通过将请求的数据字的主存储器地址发送到高速缓存系统来请求数据字。 如果高速缓存不具有信息，则高速缓存中的装置请求来自主存储器的信息，此外，该装置从连续更高的地址请求附加信息。 如果主存储器正忙，则缓存器具有要求较少字的设备。
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6.发明授权Apparatus for verifying the integrity of information stored in a data processing system memory 失效用于验证存储在数据处理系统存储器中的信息的完整性的装置
公开(公告)号：US4038537A
公开(公告)日：1977-07-26
申请号：US643453
申请日：1975-12-22
CPC分类号： G06F11/1008 , G06F11/1076 , G11C29/52
摘要： A memory having a plurality of word locations, each having a bit location, includes a parity word in one of the word locations. Bit selector means selects a column of bits made up of like positioned bits in each of the word locations. All bits in a column are added together to indicate whether there is a successful parity check. Each such column is successively checked thereby verifying the integrity of the stored information on a column basis.
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7.发明授权Firmware state apparatus for controlling sequencing of processing including test operation in multiple data lines of communication 失效用于控制包括多个数据通信线路中的测试操作的处理排序的固件状态设备
公开(公告)号：US4965721A
公开(公告)日：1990-10-23
申请号：US32896
申请日：1987-03-31
CPC分类号： G06F13/124 , H04Q3/54583
摘要： A firmware state apparatus for controlling data transfer on multiple independent data lines between a telephone communications system and computer system. At least one processor having a program counter is employed for control data transfer. A processor memory is associated with the processor and has a plurality of firmware instructions divided into groups based upon the number of predefined states which are required for performing data transfer. Certain groups of instructions include test instructions for evaluating conditions related to the line to control sequencing to a next one of the predefined states. A shared memory has a plurality of locations for line table information for at least one line with at least one location containing a program counter address specifying a starting instruction of a corresponding one of the group of instructions to be executed by the processor. The processor, in response to the group of instructions, performs a designated operation for the line and in particular in response to the test instruction loads a new value corresponding to the starting instruction of the group of instructions of the next state.
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8.发明授权Facility for passing data used by one operating system to a replacement operating system 失效将一个操作系统使用的数据传递到更换操作系统的设施
公开(公告)号：US4799145A
公开(公告)日：1989-01-17
申请号：US099698
申请日：1987-09-21
申请人： Gary J. Goss , Thomas S. Hirsch , Thomas O. Holtey
发明人： Gary J. Goss , Thomas S. Hirsch , Thomas O. Holtey
CPC分类号： G06F9/4843 , G06F9/4406 , G06F9/54
摘要： A computer system includes a first processor with main memory, an input/output processor with associated memory and an archival memory. Prior to reloading a new operating system from archival memory into the main memory, information such as timer information is stored in the input/output memory. The input/output memory continues to update the timer information until the second operating system is bootstrap loaded into the main memory. The timer and other information may then be returned to the first processor and main memory for use by the second operating system.
摘要翻译： 计算机系统包括具有主存储器的第一处理器，具有相关存储器的输入/输出处理器和档案存储器。 在将新的操作系统从归档存储器重新加载到主存储器之前，诸如定时器信息的信息被存储在输入/输出存储器中。 输入/输出存储器继续更新定时器信息，直到第二个操作系统被引导加载到主存储器中。 然后可以将定时器和其他信息返回到第一处理器和主存储器以供第二操作系统使用。
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公开(公告)号：US4703322A
公开(公告)日：1987-10-27
申请号：US946663
申请日：1987-01-05
申请人： Gary J. Goss , Thomas O. Holtey , James C. Siwik
发明人： Gary J. Goss , Thomas O. Holtey , James C. Siwik
CPC分类号： G09G5/225
摘要： A Loadable Character Generator whose operation can be changed to suit various needs, such as foreign language requirements, without hardware change and with minimum hardware. The character generator translates the character code of a character to be displayed to the dot pattern for that particular character, utilizing a minimum of hardware. The loadable character generator of the invention replaces the ROM/PROM by a RAM utilizing 2K and 8 RAM memories, a 4K by 8 memory, 4 MUX chips, and a Motorola 6845 CRT Controller with various registers and is loaded through the attribute buffer.
摘要翻译： 一种可加载字符发生器，其操作可以根据不同的需求进行更改，如外语要求，无需硬件更换和最少的硬件。 字符发生器使用最少的硬件将要显示的字符的字符代码转换为该特定字符的点阵图形。 本发明的可加载字符发生器通过RAM利用2K和8RAM存储器，4K×8存储器，4MUX芯片和具有各种寄存器的Motorola 6845 CRT控制器来代替ROM / PROM，并通过属性缓冲器加载。
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10.发明授权Communication subsystem with an automatic abort transmission upon transmit underrun 失效通信子系统在发送欠载时自动中止传输
公开(公告)号：US4418384A
公开(公告)日：1983-11-29
申请号：US194655
申请日：1980-10-06
IPC分类号： H04M11/06 , G06F13/00 , G06F13/42 , H04L1/00 , H04L1/22 , H04L29/02 , H04M11/00 , G06F3/00 , G06F11/06
CPC分类号： H04L1/0083 , G06F13/4226
摘要： A data processing system operating in a bit oriented protocol (BOP) mode of operation senses a transmit underrun; that is, the subsystem is not receiving data from a microprocessor fast enough to maintain the synchronous transmission over the communication line. Apparatus senses the transmit underrun state and generates an abort sequence of bits containing from 8 to 13 successive binary ONE bits.
摘要翻译： 以位定向协议（BOP）操作模式操作的数据处理系统感测发送欠载; 也就是说，子系统没有从微处理器接收到足够快的数据，以保持通过通信线路的同步传输。 装置感测发射欠载状态，并产生包含8到13个连续二进制1位的位的中止序列。
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