公开(公告)号：US20050272251A1

公开(公告)日：2005-12-08

申请号：US11201803

申请日：2005-08-11

申请人： Won-suk Yang ,  Ki-nam Kim

发明人： Won-suk Yang ,  Ki-nam Kim

IPC分类号： H01L21/768 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L21/336 ,  H01L21/4763

CPC分类号： H01L21/76897

摘要： An integrated circuit device, e.g., a memory device, includes a substrate, and a plurality of rows of active regions in the substrate, the active regions arranged in a staggered pattern such that active regions of a first row are aligned with portions of an isolation region separating active regions of an adjacent second row. Source and drain regions are in the active regions and are arranged such that each active region comprises a drain region disposed between two source regions. A plurality of word line structures are on the substrate, arranged transverse to the rows of active regions such that that word line structures cross the active regions between the source regions and the drain regions. Respective rows of conductive pads are disposed between respective adjacent word lines structures, including first conductive pads on the source regions, second conductive pads on the drain regions, and third conductive on isolation regions separating active regions. A plurality of bit line structures are on the substrate, extending transverse to the word line structures and contacting the second conductive pads. Related methods of fabrication are also described.

摘要翻译： 诸如存储器件的集成电路器件包括衬底以及衬底中的多行有源区域，有源区域以交错图案排列，使得第一行的有源区域与隔离的部分对准 分隔相邻第二行的有效区域的区域。 源极和漏极区域处于有源区域中并且被布置成使得每个有源区域包括设置在两个源极区域之间的漏极区域。 多个字线结构位于衬底上，横向于有源区的行布置，使得字线结构跨越源极区域和漏极区域之间的有源区域。 导电焊盘的相应行设置在相应的相邻字线结构之间，包括源区上的第一导电焊盘，漏极区上的第二导电焊盘以及分离有源区的隔离区上的第三导电。 多个位线结构在基板上，横向于字线结构延伸并与第二导电焊盘接触。 还描述了相关的制造方法。

公开(公告)号：US06806140B1

公开(公告)日：2004-10-19

申请号：US10401972

申请日：2003-03-27

申请人： Chang-Hyun Kim ,  Kyung-Ho Kim ,  Won-suk Yang

发明人： Chang-Hyun Kim ,  Kyung-Ho Kim ,  Won-suk Yang

IPC分类号： H01L21336

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

摘要： A semiconductor memory device from which a floating body effect is eliminated and which has enhanced immunity to external noise, and a method of fabricating the same are provided. The memory device includes a semiconductor substrate. A plurality of bit lines are buried in the semiconductor substrate such that the surfaces of the bit lines are adjacent to the surface of the semiconductor substrate. The bit lines are arranged in parallel with one another. A plurality of word lines are formed on the semiconductor substrate so that the word lines cross and are isolated from the bit lines. A plurality of vertical access transistors are formed at individual memory cells where the bit lines and the word lines intersect. Each vertical access transistor includes a first source/drain region, a body region including a vertical channel region and a second source/drain region which are formed sequentially on the bit line. The vertical access transistor contacts a gate insulation layer formed on a portion of one side of the sidewalls of the word line. Body regions including the channel regions of the access transistors are connected to one another to be a single integrated region.

摘要翻译： 提供了一种消除浮体效应并且具有增强的对外部噪声的抗扰性的半导体存储器件及其制造方法。 存储器件包括半导体衬底。 多个位线被埋在半导体衬底中，使得位线的表面与半导体衬底的表面相邻。 位线彼此平行排列。 多个字线形成在半导体衬底上，使得字线交叉并与位线隔离。 在位线和字线相交的各个存储单元处形成多个垂直存取晶体管。 每个垂直存取晶体管包括第一源极/漏极区域，包括在位线上顺序形成的垂直沟道区域和第二源极/漏极区域的主体区域。 垂直存取晶体管接触形成在字线侧壁一侧的一部分上的栅极绝缘层。 包括存取晶体管的通道区域的主体区域彼此连接成单个集成区域。

公开(公告)号：US06573545B2

公开(公告)日：2003-06-03

申请号：US09882489

申请日：2001-06-15

申请人： Chang-Hyun Kim ,  Kyung-Ho Kim ,  Won-suk Yang

发明人： Chang-Hyun Kim ,  Kyung-Ho Kim ,  Won-suk Yang

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

摘要： A semiconductor memory device from which a floating body effect is eliminated and which has enhanced immunity to external noise, and a method of fabricating the same are provided. The memory device includes a semiconductor substrate. A plurality of bit lines are buried in the semiconductor substrate such that the surfaces of the bit lines are adjacent to the surface of the semiconductor substrate. The bit lines are arranged in parallel with one another. A plurality of word lines are formed on the semiconductor substrate so that the word lines cross and are isolated from the bit lines. A plurality of vertical access transistors are formed at individual memory cells where the bit lines and the word lines intersect. Each vertical access transistor includes a first source/drain region, a body region including a vertical channel region and a second source/drain region which are formed sequentially on the bit line. The vertical access transistor contacts a gate insulation layer formed on a portion of one side of the sidewalls of the word line. Body regions including the channel regions of the access transistors are connected to one another to be a single integrated region.

公开(公告)号：US5358893A

公开(公告)日：1994-10-25

申请号：US118818

申请日：1993-09-10

申请人： Won-suk Yang ,  Min-uk Hwang ,  Chang-gyu Hwang

发明人： Won-suk Yang ,  Min-uk Hwang ,  Chang-gyu Hwang

IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76216 ,  H01L21/32 ,  Y10S148/117

摘要： An improved isolation method in a semiconductor device of selective polysilicon oxidation (SEPOX) which can create a field oxide layer having a size below the optical resolution and good isolation characteristics. A buffer layer comprised of polysilicon or amorphous silicon is formed on a semiconductor substrate, and then an anti-oxidative pattern with an opening which defines an isolation region exposing a portion of the buffer layer is formed. Then a portion of the exposed buffer layer is isotropically etched in order to form an undercut portion in the lower portion around the opening. Then an anti-oxidative spacer filling the undercut portion is formed on the sidewall of the opening. Thereafter, a field oxide layer is formed by partially oxidizing the portion of the buffer layer exposed by the opening and the semiconductor substrate exposed in the opening. The size of bird's beak is decreased, thereby forming a field oxide layer with good isolation characteristics and small size.

摘要翻译： 在选择性多晶硅氧化（SEPOX）的半导体器件中的改进的隔离方法，其可以产生尺寸低于光学分辨率和良好隔离特性的场氧化物层。 在半导体衬底上形成由多晶硅或非晶硅组成的缓冲层，然后形成具有限定了缓冲层的一部分的隔离区的开口的抗氧化图案。 然后，暴露的缓冲层的一部分被各向同性蚀刻，以便在开口周围的下部形成底切部分。 然后在开口的侧壁上形成填充底切部分的抗氧化间隔物。 此后，通过部分氧化由开口暴露的缓冲层的部分和暴露在开口中的半导体衬底而形成场氧化物层。 鸟喙的尺寸减小，形成具有良好隔离特性和小尺寸的场氧化物层。

公开(公告)号：US5296410A

公开(公告)日：1994-03-22

申请号：US992963

申请日：1992-12-16

申请人： Won-suk Yang

发明人： Won-suk Yang

IPC分类号： H01L21/033 ,  H01L21/316

CPC分类号： H01L21/0338 ,  H01L21/0337 ,  Y10S438/942 ,  Y10S438/947

摘要： A method for forming a fine pattern of a semiconductor device, in which a first-to-be-patterned layer is formed on a semiconductor substrate, a photoresist film is coated on the first-to-be-patterned layer, and the photoresist film is patterned and cured to obtain a thermally stable photoresist film pattern. Thereafter, a second material layer is formed on the entire surface of the semiconductor substrate on which the photoresist film pattern is formed, by a low temperature plasma method, and the second material layer is anisotropically etched to thereby form a spacer made of the second material layer on the sidewalls of the photoresist film pattern. A first pattern is formed by anisotropically etching the first-to-be-patterned layer, using the spacer and the photoresist film pattern as an etching mask. The spacer and the photoresist film pattern are then removed. Using the first pattern thus obtained, a fine pattern which is the inverse of the first pattern can be formed. The separation interval between the individual elements can be reduced so as to be less than or equal to the minimum design rule, and a fine pattern below optical resolution can be attained.

摘要翻译： 一种形成半导体器件的精细图案的方法，其中在半导体衬底上形成第一待图案化层，在第一待图案层上涂覆光致抗蚀剂膜，并且光刻胶膜 被图案化和固化以获得热稳定的光致抗蚀剂膜图案。 此后，通过低温等离子体法在形成有光致抗蚀剂膜图案的半导体基板的整个表面上形成第二材料层，并且第二材料层被各向异性地蚀刻从而形成由第二材料制成的间隔物 在光致抗蚀剂膜图案的侧壁上。 通过使用间隔物和光致抗蚀剂膜图案作为蚀刻掩模，通过各向异性蚀刻第一待图案化层来形成第一图案。 然后去除间隔物和光致抗蚀剂膜图案。 使用如此获得的第一图案，可以形成与第一图案相反的精细图案。 各个元件之间的分离间隔可以减小到小于或等于最小设计规则，并且可以获得低于光学分辨率的精细图案。