公开(公告)号：US12066969B2

公开(公告)日：2024-08-20

申请号：US17589633

申请日：2022-01-31

Applicant: XILINX, INC.

Inventor： Krishnan Srinivasan ,  Sagheer Ahmad ,  Ygal Arbel ,  Millind Mittal

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/40

CPC classification number: G06F13/42 ,  G06F13/382 ,  G06F13/4063

Abstract: Embodiments herein describe using an adaptive chip-to-chip (C2C) interface to interconnect two chips, wherein the adaptive C2C interface includes circuitry for performing multiple different C2C protocols to communicate with the other chip. One or both of the chips in the C2C connection can include the adaptive C2C interface. During boot time, the adaptive C2C interface is configured to perform one of the different C2C protocols. During runtime, the chip then uses the selected C2C protocol to communicate with the other chip in the C2C connection.

公开(公告)号：US11887558B1

公开(公告)日：2024-01-30

申请号：US18144692

申请日：2023-05-08

Applicant: XILINX, INC.

Inventor： Krishnan Srinivasan ,  Qingyi Sheng ,  Kam-Wang Li

IPC: G09G5/00

CPC classification number: G09G5/003 ,  G09G2310/0264 ,  G09G2360/122

Abstract: An integrated circuit (IC) includes a video buffer memory and display driver circuitry. The video buffer memory includes a buffer memory map. The video buffer memory stores one or more raster lines of video data organized as tiled lines. Each of the tiled lines including two quartiles. The display driver circuitry is coupled to the video buffer memory. The display driver circuitry writes data associated with a portion of a first data line to a first one of the two quartiles of a first one of the tiled lines, and updates the buffer memory map. Further, the display driver determines a full display line being present within the video buffer memory based on the buffer memory map. The display driver further outputs the full display line to a display device.

公开(公告)号：US20230370392A1

公开(公告)日：2023-11-16

申请号：US17663376

申请日：2022-05-13

Applicant: Xilinx, Inc.

Inventor： Krishnan Srinivasan ,  Sagheer Ahmad ,  Ygal Arbel ,  Aman Gupta

IPC: H04L49/109

CPC classification number: H04L49/109

Abstract: An integrated circuit (IC) includes a Network-on-Chip (NoC). The NoC includes a plurality of NoC master circuits, a plurality of NoC slave circuits, and a plurality of switches. The plurality of switches are interconnected and communicatively link the plurality of NoC master circuits with the plurality of NoC slave circuits. The plurality of switches are configured to receive data of different widths during operation and implement different operating modes for forwarding the data based on the different widths.

公开(公告)号：US11755511B2

公开(公告)日：2023-09-12

申请号：US17411891

申请日：2021-08-25

Applicant: XILINX, INC.

Inventor： Krishnan Srinivasan ,  Sagheer Ahmad

IPC: G06F13/20 ,  G06F9/445

CPC classification number: G06F13/20 ,  G06F9/44505

Abstract: Transmitter circuitry includes inversion circuitry, first transform circuitry, and selection circuitry. The inversion circuitry generates a first transformed data word by inverting one or more of a plurality of bits of a first data word. The first transform circuitry generates a second transformed data word by performing a first invertible operation on the first data word and a second data word. The selection circuitry selects one of the first data word, the first transformed data word, and the second transformed data word based on a first number of bit inversions between the first data word and the second data word, a second number of bit inversions between the first transformed data word and the second data word, and a third number of bit inversions between the second transformed data word and the second data word. The selection circuitry further outputs the selected data word.