公开(公告)号：US11983122B2

公开(公告)日：2024-05-14

申请号：US17660799

申请日：2022-04-26

申请人： Xilinx, Inc.

发明人： David K. Liddell ,  Sachin Kumawat

IPC分类号： G06F12/126 ,  G06F12/02 ,  G06F12/0853

CPC分类号： G06F12/126 ,  G06F12/0292 ,  G06F12/0853

摘要： A system includes a multi-port RAM configured to store an instruction table. The instruction table specifies a regular expression for application to a data stream. The system includes a regular expression engine (engine) that processes the data stream using the instruction table. The engine includes a decoder circuit that determines validity of active states output from the multi-port RAM and a plurality of priority FIFO memories (PFIFOs) operating concurrently. Each PFIFO can initiate a read from a different port of the multi-port RAM. Each PFIFO can track a plurality of active paths for the regular expression and a priority of each active path by, at least in part, storing entries corresponding to active states in each respective PFIFO in decreasing priority order. The engine includes switching circuitry that selectively routes the active states from the decoder circuit to the plurality of PFIFOs according to the priority order.

公开(公告)号：US11816335B1

公开(公告)日：2023-11-14

申请号：US17660808

申请日：2022-04-26

申请人： Xilinx, Inc.

发明人： Sachin Kumawat ,  David K. Liddell ,  Paul R. Schumacher

IPC分类号： G06F3/06

CPC分类号： G06F3/061 ,  G06F3/0655 ,  G06F3/0673

摘要： A system includes a first multi-port RAM storing an instruction table. The instruction table specifies a regular expression for application to a data stream and a second multi-port RAM configured to store a capture table having capture entries decodable for tracking position information for a sequence of characters matching a capture sub-expression of the regular expression. The system includes a regular expression engine processing the data stream to determine match states by tracking active states for the regular expression and priorities for the active states by storing the active states of the regular expression in a plurality of priority FIFO memories in decreasing priority order. The system includes a capture engine operating in coordination with the regular expression engine to determine character(s) of the data stream that match the capture sub-expression based on the active state being tracked and decoding the capture entries of the capture table.

公开(公告)号：US11042564B1

公开(公告)日：2021-06-22

申请号：US16145013

申请日：2018-09-27

申请人： Xilinx, Inc.

发明人： David K. Liddell ,  Roger Ng ,  Kumar Deepak

IPC分类号： G06F16/26 ,  G06T11/20 ,  G06F9/46 ,  G06F16/248 ,  G06F16/23 ,  G06F3/0484 ,  G06T11/60

摘要： Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating transaction associations in a waveform display. One of the methods includes receiving data representing a main signal for a selected transaction in a waveform display, the main signal including a plurality of main signal events. A search is performed for data representing one or more side signals associated with the main signal for the selected transaction, each side signal including a plurality of side signal events representing other transactions that are associated with the main signal at a time indicated by a corresponding main signal event. A visual indication is generated within the waveform display of an association between the selected transaction and one or more transactions identified by the one or more side signals associated with the main signal for the selected transaction.