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公开(公告)号：US09582619B1
公开(公告)日：2017-02-28
申请号：US14058505
申请日：2013-10-21
申请人： Xilinx, Inc.
发明人： David K. Liddell , Feng Cai , Saikat Bandyopadhyay
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5045
摘要： An approach for simulating a block of a circuit design includes using a row-matching table and a port state vector. The row-matching table includes a plurality of rows, and each row includes encoded input match patterns corresponding to a plurality of input ports of the block and an associated output value. The port state vector includes input state codes associated with the input ports. In response to an update of an input signal value at one of the input ports during simulation, the input state code associated with the one input port is updated according to the updated input signal value. A bit-to-bit pattern match is performed for each bit in the port state vector to a corresponding bit in the encoded input match patterns in one or more rows of the row-matching table. The associated output value of a matching row is selected as a new output value.
摘要翻译： 用于模拟电路设计的块的方法包括使用行匹配表和端口状态向量。 行匹配表包括多行，并且每行包括与块的多个输入端口对应的编码输入匹配模式和相关联的输出值。 端口状态向量包括与输入端口相关联的输入状态代码。 响应于在模拟期间在输入端口之一处的输入信号值的更新，与一个输入端口相关联的输入状态代码根据更新的输入信号值被更新。 对端口状态向量中的每个位执行位对位模式匹配，使其与行匹配表的一行或多行中的编码输入匹配模式中的相应位相对应。 匹配行的关联输出值被选为新的输出值。
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2.发明授权公开(公告)号：US09223910B1
公开(公告)日：2015-12-29
申请号：US14159855
申请日：2014-01-21
申请人： Xilinx, Inc.
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method for compiling an HDL specification for simulation of a circuit design is disclosed. The circuit design is elaborated from the HDL specification and memory locations are allocated for formals and actuals of the elaborated circuit design. For each port having a formal and an actual that are compatible, the allocating of memory locations sets a reference pointer for the formal and a reference pointer for the actual to reference a same one of the memory locations. For each port having a formal and an actual that are incompatible, the allocating of memory locations sets the reference pointer for the formal and the reference pointer for the actual to reference different respective ones of the memory locations. Simulation code modeling the elaborated circuit design is generated that updates a formal and actual of a port that are compatible using a single write operation to the referenced memory location.
摘要翻译： 公开了一种用于编译用于模拟电路设计的HDL规范的方法。 电路设计由HDL规范进行阐述，内存位置分配给精密电路设计的正式和实际。 对于具有兼容的形式和实际的每个端口，存储器位置的分配设置用于形式的参考指针和用于实际引用相同存储器位置的引用指针。 对于具有不兼容的形式和实际的每个端口，存储器位置的分配设置形式的参考指针和用于实际引用的参考指针以引用不同的相应存储器位置。 生成针对详细电路设计的仿真代码建模，其将使用单个写入操作兼容的端口的正式和实际更新到引用的存储器位置。
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公开(公告)号：US10762263B1
公开(公告)日：2020-09-01
申请号：US15988293
申请日：2018-05-24
申请人： Xilinx, Inc.
发明人： Roger Ng , David K. Liddell
IPC分类号： G06F30/3312 , G06F30/367 , G06F119/12
摘要： A method includes inputting to a computer processor a search value. Bit values of bit element signals of a bus at a current time are determined time-ordered value pairs of timestamps and associated bit values of the bit element signals. Whether the bit values at the current time match values of corresponding bits of the search value is determined from the time-ordered value pairs. Data indicative of the current time and bit values of the bit element signals is output if the bit values at the current time match the search value. If any of the bit values at the current time do not match the search value, the current time is advanced to a later time indicated by a time-ordered value pair not matched to the search value and having a latest timestamp of the bit element signals that do not match corresponding bits of the search value.
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公开(公告)号：US20230342068A1
公开(公告)日：2023-10-26
申请号：US17660801
申请日：2022-04-26
申请人： Xilinx, Inc.
发明人： Sachin Kumawat , David K. Liddell , Jiayou Wang
IPC分类号： G06F3/06
CPC分类号： G06F3/0655 , G06F3/0614 , G06F3/0673
摘要： A system includes a multi-port random-access memory (RAM) configured to store an instruction table. The instruction table specifies a regular expression for application to a data stream. The system includes a regular expression engine configured to process the data stream based on the instruction table. The regular expression engine includes a decoder circuit configured to determine validity of active states output from the RAM, a plurality of active states memories operating concurrently, wherein each active states memory is configured to initiate a read from a different port of the RAM using an address formed of an active state output from the active states memory and a portion of the data stream, and switching circuitry configured to route the active states to the plurality of active states memories according, at least in part, to a load balancing technique and validity of the active states.
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公开(公告)号：US10816600B1
公开(公告)日：2020-10-27
申请号：US15824789
申请日：2017-11-28
申请人： Xilinx, Inc.
IPC分类号： G01R31/3183 , G01R31/28 , G06F30/33 , G01R31/3193
摘要： Protocol analysis can include simulating, using a processor, a circuit design including a protocol analyzer embedded therein. The protocol analyzer can be coupled to low-level signals of an interface of the circuit design. During the simulating, the protocol analyzer detects a transaction from the low-level signals received from the interface. Transaction data is generated by the protocol analyzer specifying the transaction. The transaction data is output from the protocol analyzer.
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公开(公告)号：US10740210B1
公开(公告)日：2020-08-11
申请号：US15824631
申请日：2017-11-28
申请人： Xilinx, Inc.
发明人： Paul R. Schumacher , Kumar Deepak , Roger Ng , David K. Liddell
摘要： Tracing operation of a kernel can include comparing, using a processor, signals of a compiled kernel with a database including compiler generated signals for compute units to determine a list of the signals of the compiled kernel that match the compiler generated signals and generating trace data by emulating the compiled kernel using the processor. The trace data includes values for signals of the compiled kernel collected over time during the emulation. Operational data corresponding to individual compute units of the compiled kernel can be determined from values of the signals of the list within the trace data using the processor. The operational data can be displayed using the processor.
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公开(公告)号：US11861171B2
公开(公告)日：2024-01-02
申请号：US17660808
申请日：2022-04-26
申请人： Xilinx, Inc.
IPC分类号： G06F3/06
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0673
摘要： A system includes a first multi-port RAM storing an instruction table. The instruction table specifies a regular expression for application to a data stream and a second multi-port RAM configured to store a capture table having capture entries decodable for tracking position information for a sequence of characters matching a capture sub-expression of the regular expression. The system includes a regular expression engine processing the data stream to determine match states by tracking active states for the regular expression and priorities for the active states by storing the active states of the regular expression in a plurality of priority FIFO memories in decreasing priority order. The system includes a capture engine operating in coordination with the regular expression engine to determine character(s) of the data stream that match the capture sub-expression based on the active state being tracked and decoding the capture entries of the capture table.
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8.发明公开公开(公告)号：US20230342304A1
公开(公告)日：2023-10-26
申请号：US17660799
申请日：2022-04-26
申请人： Xilinx, Inc.
发明人： David K. Liddell , Sachin Kumawat
IPC分类号： G06F12/126 , G06F12/02 , G06F12/0853
CPC分类号： G06F12/126 , G06F12/0292 , G06F12/0853
摘要： A system includes a multi-port RAM configured to store an instruction table. The instruction table specifies a regular expression for application to a data stream. The system includes a regular expression engine (engine) that processes the data stream using the instruction table. The engine includes a decoder circuit that determines validity of active states output from the multi-port RAM and a plurality of priority FIFO memories (PFIFOs) operating concurrently. Each PFIFO can initiate a read from a different port of the multi-port RAM. Each PFIFO can track a plurality of active paths for the regular expression and a priority of each active path by, at least in part, storing entries corresponding to active states in each respective PFIFO in decreasing priority order. The engine includes switching circuitry that selectively routes the active states from the decoder circuit to the plurality of PFIFOs according to the priority order.
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9.发明公开公开(公告)号：US20230342030A1
公开(公告)日：2023-10-26
申请号：US17660808
申请日：2022-04-26
申请人： Xilinx, Inc.
IPC分类号： G06F3/06
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0673
摘要： A system includes a first multi-port RAM storing an instruction table. The instruction table specifies a regular expression for application to a data stream and a second multi-port RAM configured to store a capture table having capture entries decodable for tracking position information for a sequence of characters matching a capture sub-expression of the regular expression. The system includes a regular expression engine processing the data stream to determine match states by tracking active states for the regular expression and priorities for the active states by storing the active states of the regular expression in a plurality of priority FIFO memories in decreasing priority order. The system includes a capture engine operating in coordination with the regular expression engine to determine character(s) of the data stream that match the capture sub-expression based on the active state being tracked and decoding the capture entries of the capture table.
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公开(公告)号：US12014072B2
公开(公告)日：2024-06-18
申请号：US17660801
申请日：2022-04-26
申请人： Xilinx, Inc.
发明人： Sachin Kumawat , David K. Liddell , Jiayou Wang
CPC分类号： G06F3/0655 , G06F3/0614 , G06F3/0673 , G06F11/1629 , G06F2207/025
摘要： A system includes a multi-port random-access memory (RAM) configured to store an instruction table. The instruction table specifies a regular expression for application to a data stream. The system includes a regular expression engine configured to process the data stream based on the instruction table. The regular expression engine includes a decoder circuit configured to determine validity of active states output from the RAM, a plurality of active states memories operating concurrently, wherein each active states memory is configured to initiate a read from a different port of the RAM using an address formed of an active state output from the active states memory and a portion of the data stream, and switching circuitry configured to route the active states to the plurality of active states memories according, at least in part, to a load balancing technique and validity of the active states.
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