公开(公告)号：US09183334B1

公开(公告)日：2015-11-10

申请号：US14323829

申请日：2014-07-03

Applicant: Xilinx, Inc.

Inventor： Xiaoyang Zhang ,  Adam P. Donlin ,  Kyle Corbett ,  Khang K. Dao

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5045 ,  G06F2217/14

Abstract: Approaches for verifying connectivity of signals in a circuit design include generating a configured version of the circuit design based on input parameter values. The configured version specifies connections from source pins of ports of circuit blocks of the configured version to destination pins of ports of circuit blocks. Expected source-destination connections between source pins and destination pins of the ports of the circuit blocks of the configured version are determined from the input parameter values. A connectivity checker that includes HDL code is generated based on the expected source-destination connections. For each of the expected source-destination connections, the HDL code forces a first signal value on a source pin of the expected source-destination connection in the configured version of the circuit design and determines whether or not a second signal value at a destination pin of the expected source-destination connection matches the first signal value.

Abstract translation: 用于验证电路设计中信号的连通性的方法包括基于输入参数值生成电路设计的配置版本。 配置的版本指定从配置版本的电路块的端口的源引脚到电路块端口的目标引脚的连接。 根据输入参数值确定配置版本的电路块端口的源引脚和目标引脚之间的预期源 - 目标连接。 包含HDL代码的连接检查程序是根据预期的源 - 目标连接生成的。 对于每个预期的源 - 目的地连接，HDL代码强制在电路设计的配置版本中期望的源 - 目的地连接的源引脚上的第一信号值，并确定目的地引脚上的第二信号值 的预期源 - 目的地连接符合第一信号值。

公开(公告)号：US08769449B1

公开(公告)日：2014-07-01

申请号：US13763317

申请日：2013-02-08

Applicant: Xilinx, Inc.

Inventor： Adam P. Donlin ,  Biping Wu ,  Kyle Corbett ,  Nabeel Shirazi ,  Shay P. Seng ,  Amit Kasat ,  Srinivas Beeravolu ,  Khang K. Dao ,  Jeffrey H. Seltzer ,  Christopher J. Case

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F2217/66

Abstract: Methods for generating a circuit design are disclosed. A plurality of cells is instantiated in the circuit design in response to user input. The set of interface parameters of each cell is arranged into a hierarchy of interface levels as indicated by an interface model corresponding to the cell. For each of the interface levels, values of the sets of interface parameters of cells included in the interface level are respectively propagated to other cells directly connected to the cell. In response to propagating a value of an interface parameter from another cell of the plurality of cells to the cell and the cell having a value of the corresponding interface parameter that is different from the propagated value, a value for the corresponding interface parameter of the cell is determined using a respective propagation function associated with the corresponding interface level.

Abstract translation: 公开了用于产生电路设计的方法。 响应于用户输入，在电路设计中实例化多个单元。 每个单元的接口参数的集合被布置成如由与该单元相对应的接口模型所指示的接口层级。 对于每个接口级别，包括在接口级别中的单元的接口参数的集合的值分别传播到直接连接到该单元的其他单元。 响应于将接口参数的值从多个小区的另一小区传播到小区，并且具有与传播值不同的对应接口参数的小区的小区响应于小区的对应接口参数的值 使用与对应的接口电平相关联的相应传播函数来确定。