公开(公告)号：US11204747B1

公开(公告)日：2021-12-21

申请号：US15786395

申请日：2017-10-17

Applicant: Xilinx, Inc.

Inventor： Jindrich Zejda ,  Elliott Delaye ,  Yongjun Wu ,  Aaron Ng ,  Ashish Sirasao ,  Khang K. Dao ,  Christopher J. Case

IPC: G06F9/45 ,  G06F8/41 ,  G06N3/02 ,  G06F13/28 ,  G06F8/30 ,  G06F9/451 ,  G06F9/50 ,  G06F13/362

Abstract: Embodiments herein describe techniques for interfacing a neural network application with a neural network accelerator that operate on two heterogeneous computing systems. For example, the neural network application may execute on a central processing unit (CPU) in a computing system while the neural network accelerator executes on a FPGA. As a result, when moving a software-hardware boundary between the two heterogeneous systems, changes may be made to both the neural network application (using software code) and to the accelerator (using RTL). The embodiments herein describe a software defined approach where shared interface code is used to express both sides of the interface between the two heterogeneous systems in a single abstraction (e.g., a software class).

公开(公告)号：US10802995B2

公开(公告)日：2020-10-13

申请号：US16046602

申请日：2018-07-26

Applicant: Xilinx, Inc.

Inventor： Sarabjeet Singh ,  Hem C. Neema ,  Sonal Santan ,  Khang K. Dao ,  Kyle Corbett ,  Yi Wang ,  Christopher J. Case

IPC: G06F9/38 ,  G06F13/16 ,  G06F9/46 ,  G06F12/0873 ,  G06F12/1045 ,  G06F12/1081

Abstract: A system may include a host processor coupled to a communication bus, a first hardware accelerator communicatively linked to the host processor through the communication bus, and a second hardware accelerator communicatively linked to the host processor through the communication bus. The first hardware accelerator and the second hardware accelerator are directly coupled through an accelerator link independent of the communication bus. The host processor is configured to initiate a data transfer between the first hardware accelerator and the second hardware accelerator directly through the accelerator link.

公开(公告)号：US20200081850A1

公开(公告)日：2020-03-12

申请号：US16046602

申请日：2018-07-26

Applicant: Xilinx, Inc.

Inventor： Sarabjeet Singh ,  Hem C. Neema ,  Sonal Santan ,  Khang K. Dao ,  Kyle Corbett ,  Yi Wang ,  Christopher J. Case

IPC: G06F13/16 ,  G06F12/1045 ,  G06F12/0873 ,  G06F12/1081 ,  G06F9/46

Abstract: A system may include a host processor coupled to a communication bus, a first hardware accelerator communicatively linked to the host processor through the communication bus, and a second hardware accelerator communicatively linked to the host processor through the communication bus. The first hardware accelerator and the second hardware accelerator are directly coupled through an accelerator link independent of the communication bus. The host processor is configured to initiate a data transfer between the first hardware accelerator and the second hardware accelerator directly through the accelerator link.

公开(公告)号：US20230098098A1

公开(公告)日：2023-03-30

申请号：US17487781

申请日：2021-09-28

Applicant: Xilinx, Inc.

Inventor： Adam P. Donlin ,  Kyle Corbett ,  Christopher J. Case

IPC: G06F30/392 ,  G06F30/398 ,  G06F30/31

Abstract: Using scalable scribe regions for implementing a user circuit design includes generating a scribe region having a plurality of contours for a static top design of a circuit design for an integrated circuit. The static top design is configured to integrate with a user circuit design in the integrated circuit. Each contour defines a different size of the scribe region having a boundary that extends outward in at least one direction from a boundary of a floorplan area of the static top design on the IC. The scribe region can be translated into design constraints defining the plurality of contours of the scribe region and restrict placement of components of the user circuit design within the scribe region as sized according to a selected contour. The static top design and the plurality of design constraints can be stored in a memory for use in implementing the user circuit design.

公开(公告)号：US11610042B1

公开(公告)日：2023-03-21

申请号：US17487781

申请日：2021-09-28

Applicant: Xilinx, Inc.

Inventor： Adam P. Donlin ,  Kyle Corbett ,  Christopher J. Case

IPC: G06F30/392 ,  G06F30/31 ,  G06F30/398 ,  G06F111/20

Abstract: Using scalable scribe regions for implementing a user circuit design includes generating a scribe region having a plurality of contours for a static top design of a circuit design for an integrated circuit. The static top design is configured to integrate with a user circuit design in the integrated circuit. Each contour defines a different size of the scribe region having a boundary that extends outward in at least one direction from a boundary of a floorplan area of the static top design on the IC. The scribe region can be translated into design constraints defining the plurality of contours of the scribe region and restrict placement of components of the user circuit design within the scribe region as sized according to a selected contour. The static top design and the plurality of design constraints can be stored in a memory for use in implementing the user circuit design.

公开(公告)号：US08769449B1

公开(公告)日：2014-07-01

申请号：US13763317

申请日：2013-02-08

Applicant: Xilinx, Inc.

Inventor： Adam P. Donlin ,  Biping Wu ,  Kyle Corbett ,  Nabeel Shirazi ,  Shay P. Seng ,  Amit Kasat ,  Srinivas Beeravolu ,  Khang K. Dao ,  Jeffrey H. Seltzer ,  Christopher J. Case

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F2217/66

Abstract: Methods for generating a circuit design are disclosed. A plurality of cells is instantiated in the circuit design in response to user input. The set of interface parameters of each cell is arranged into a hierarchy of interface levels as indicated by an interface model corresponding to the cell. For each of the interface levels, values of the sets of interface parameters of cells included in the interface level are respectively propagated to other cells directly connected to the cell. In response to propagating a value of an interface parameter from another cell of the plurality of cells to the cell and the cell having a value of the corresponding interface parameter that is different from the propagated value, a value for the corresponding interface parameter of the cell is determined using a respective propagation function associated with the corresponding interface level.

Abstract translation: 公开了用于产生电路设计的方法。 响应于用户输入，在电路设计中实例化多个单元。 每个单元的接口参数的集合被布置成如由与该单元相对应的接口模型所指示的接口层级。 对于每个接口级别，包括在接口级别中的单元的接口参数的集合的值分别传播到直接连接到该单元的其他单元。 响应于将接口参数的值从多个小区的另一小区传播到小区，并且具有与传播值不同的对应接口参数的小区的小区响应于小区的对应接口参数的值 使用与对应的接口电平相关联的相应传播函数来确定。