公开(公告)号：US11922223B1

公开(公告)日：2024-03-05

申请号：US17170427

申请日：2021-02-08

Applicant: Xilinx, Inc.

Inventor： Adam P. Donlin ,  Kyle Corbett ,  Lizhi Hou ,  Julian M. Kain

IPC: G06F9/50 ,  G06F9/38 ,  H04L9/06

CPC classification number: G06F9/5077 ,  G06F9/3836 ,  G06F9/3877 ,  H04L9/0643

Abstract: Control of a reconfigurable platform can include determining, by a host computer, an interface universally unique identifier (UUID) of an interface of platform circuitry implemented on an accelerator, wherein the accelerator is communicatively linked to the host computer. An electronic request to run a partition design on the accelerator is received by the host computer. In response to the electronic request, the host computer determines an interface UUID for an interface of the partition design and determines compatibility of the partition design with the platform circuitry based on a comparison of the interface UUID of the partition design with the interface UUID of the platform circuitry. The partition design is implemented on the accelerator in response to determining that the partition design is compatible with the platform circuitry.

公开(公告)号：US08775987B1

公开(公告)日：2014-07-08

申请号：US13946137

申请日：2013-07-19

Applicant: Xilinx, Inc.

Inventor： Adam P. Donlin ,  Kyle Corbett

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5045 ,  G06F2217/02 ,  G06F2217/66

Abstract: Approaches are disclosed for testing a module of a circuit design. The module is simulated a first time using a testbench on a programmed processor. Event data is captured to a first file during the simulating. For each event, the event data describes a signal identifier, an associated signal value, and an associated timestamp. The event data of the first file is transformed into a hardware description language (HDL) replay module.

Abstract translation: 公开了用于测试电路设计的模块的方法。 首先使用编程处理器上的测试台模拟模块。 在模拟期间，事件数据被捕获到第一个文件。 对于每个事件，事件数据描述信号标识符，相关联的信号值和相关联的时间戳。 第一个文件的事件数据被转换成硬件描述语言（HDL）重放模块。

公开(公告)号：US11232247B1

公开(公告)日：2022-01-25

申请号：US17075364

申请日：2020-10-20

Applicant: Xilinx, Inc.

Inventor： Julian M. Kain ,  Adam P. Donlin

IPC: G06F30/39 ,  G06F9/54 ,  G06F9/38 ,  G06F30/34

Abstract: Creating an adaptable dynamic region for hardware acceleration can include receiving a first kernel for inclusion in a circuit design for an integrated circuit of an accelerator platform. The circuit design includes a dynamic design corresponding to a dynamic region of programmable circuitry in the integrated circuit that couples to a static region of the programmable circuitry. The first kernel can be included in the within the dynamic design. A global resource used by the first kernel can be determined. An interconnect architecture for the dynamic design can be constructed based on the global resource used by the first kernel.

公开(公告)号：US10817353B1

公开(公告)日：2020-10-27

申请号：US16225279

申请日：2018-12-19

Applicant: Xilinx, Inc.

Inventor： Julian M. Kain ,  Adam P. Donlin

IPC: G06F30/34 ,  G06F9/54 ,  G06F9/38 ,  G06F30/39

Abstract: Creating an adaptable dynamic region for hardware acceleration can include receiving a first kernel for inclusion in a circuit design for an integrated circuit of an accelerator platform. The circuit design includes a dynamic design corresponding to a dynamic region of programmable circuitry in the integrated circuit that couples to a static region of the programmable circuitry. The first kernel can be included in the within the dynamic design. A global resource used by the first kernel can be determined. An interconnect architecture for the dynamic design can be constructed based on the global resource used by the first kernel.

公开(公告)号：US20230098098A1

公开(公告)日：2023-03-30

申请号：US17487781

申请日：2021-09-28

Applicant: Xilinx, Inc.

Inventor： Adam P. Donlin ,  Kyle Corbett ,  Christopher J. Case

IPC: G06F30/392 ,  G06F30/398 ,  G06F30/31

Abstract: Using scalable scribe regions for implementing a user circuit design includes generating a scribe region having a plurality of contours for a static top design of a circuit design for an integrated circuit. The static top design is configured to integrate with a user circuit design in the integrated circuit. Each contour defines a different size of the scribe region having a boundary that extends outward in at least one direction from a boundary of a floorplan area of the static top design on the IC. The scribe region can be translated into design constraints defining the plurality of contours of the scribe region and restrict placement of components of the user circuit design within the scribe region as sized according to a selected contour. The static top design and the plurality of design constraints can be stored in a memory for use in implementing the user circuit design.

公开(公告)号：US11610042B1

公开(公告)日：2023-03-21

申请号：US17487781

申请日：2021-09-28

Applicant: Xilinx, Inc.

Inventor： Adam P. Donlin ,  Kyle Corbett ,  Christopher J. Case

IPC: G06F30/392 ,  G06F30/31 ,  G06F30/398 ,  G06F111/20

Abstract: Using scalable scribe regions for implementing a user circuit design includes generating a scribe region having a plurality of contours for a static top design of a circuit design for an integrated circuit. The static top design is configured to integrate with a user circuit design in the integrated circuit. Each contour defines a different size of the scribe region having a boundary that extends outward in at least one direction from a boundary of a floorplan area of the static top design on the IC. The scribe region can be translated into design constraints defining the plurality of contours of the scribe region and restrict placement of components of the user circuit design within the scribe region as sized according to a selected contour. The static top design and the plurality of design constraints can be stored in a memory for use in implementing the user circuit design.

公开(公告)号：US09183334B1

公开(公告)日：2015-11-10

申请号：US14323829

申请日：2014-07-03

Applicant: Xilinx, Inc.

Inventor： Xiaoyang Zhang ,  Adam P. Donlin ,  Kyle Corbett ,  Khang K. Dao

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5045 ,  G06F2217/14

Abstract: Approaches for verifying connectivity of signals in a circuit design include generating a configured version of the circuit design based on input parameter values. The configured version specifies connections from source pins of ports of circuit blocks of the configured version to destination pins of ports of circuit blocks. Expected source-destination connections between source pins and destination pins of the ports of the circuit blocks of the configured version are determined from the input parameter values. A connectivity checker that includes HDL code is generated based on the expected source-destination connections. For each of the expected source-destination connections, the HDL code forces a first signal value on a source pin of the expected source-destination connection in the configured version of the circuit design and determines whether or not a second signal value at a destination pin of the expected source-destination connection matches the first signal value.

Abstract translation: 用于验证电路设计中信号的连通性的方法包括基于输入参数值生成电路设计的配置版本。 配置的版本指定从配置版本的电路块的端口的源引脚到电路块端口的目标引脚的连接。 根据输入参数值确定配置版本的电路块端口的源引脚和目标引脚之间的预期源 - 目标连接。 包含HDL代码的连接检查程序是根据预期的源 - 目标连接生成的。 对于每个预期的源 - 目的地连接，HDL代码强制在电路设计的配置版本中期望的源 - 目的地连接的源引脚上的第一信号值，并确定目的地引脚上的第二信号值 的预期源 - 目的地连接符合第一信号值。

公开(公告)号：US08769449B1

公开(公告)日：2014-07-01

申请号：US13763317

申请日：2013-02-08

Applicant: Xilinx, Inc.

Inventor： Adam P. Donlin ,  Biping Wu ,  Kyle Corbett ,  Nabeel Shirazi ,  Shay P. Seng ,  Amit Kasat ,  Srinivas Beeravolu ,  Khang K. Dao ,  Jeffrey H. Seltzer ,  Christopher J. Case

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F2217/66

Abstract: Methods for generating a circuit design are disclosed. A plurality of cells is instantiated in the circuit design in response to user input. The set of interface parameters of each cell is arranged into a hierarchy of interface levels as indicated by an interface model corresponding to the cell. For each of the interface levels, values of the sets of interface parameters of cells included in the interface level are respectively propagated to other cells directly connected to the cell. In response to propagating a value of an interface parameter from another cell of the plurality of cells to the cell and the cell having a value of the corresponding interface parameter that is different from the propagated value, a value for the corresponding interface parameter of the cell is determined using a respective propagation function associated with the corresponding interface level.

Abstract translation: 公开了用于产生电路设计的方法。 响应于用户输入，在电路设计中实例化多个单元。 每个单元的接口参数的集合被布置成如由与该单元相对应的接口模型所指示的接口层级。 对于每个接口级别，包括在接口级别中的单元的接口参数的集合的值分别传播到直接连接到该单元的其他单元。 响应于将接口参数的值从多个小区的另一小区传播到小区，并且具有与传播值不同的对应接口参数的小区的小区响应于小区的对应接口参数的值 使用与对应的接口电平相关联的相应传播函数来确定。