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    Memory utilization in a circuit design
    2.
    发明授权
    Memory utilization in a circuit design 有权

    公开(公告)号：US09792395B1

    公开(公告)日：2017-10-17

    申请号：US15013196

    申请日：2016-02-02

    Applicant: Xilinx, Inc.

    Inventor： Jayaram Pvss ,  Robert Bellarmin Susai ,  Khang K. Dao

    IPC: G06F17/50

    CPC classification number: G06F17/505

    Abstract: The disclosed approaches compile a hierarchical representation of a circuit design into a flattened netlist and store the flattened netlist a memory circuit. The circuit design instantiates a plurality of memory blocks of a target device and specifies logic circuits that access the plurality of memory blocks, respectively. The flattened netlist is modified by determining a subset of the plurality of memory blocks. The quantity of memory reserved in each memory block of the subset is less than a capacity of said each memory block. One memory block is instantiated, for a pair of the memory blocks of the subset, in place of each memory block of the pair in the flattened netlist in the memory circuit. A portion of the flattened netlist that specifies the logic circuits that access each memory block of the pair is modified to access the one memory block instead of each memory block of the pair.

    Debugging using tagged flip-flops
    3.
    发明授权
    Debugging using tagged flip-flops 有权
    使用标记的触发器进行调试

    公开(公告)号：US08813005B1

    公开(公告)日：2014-08-19

    申请号：US14016941

    申请日：2013-09-03

    Applicant: Xilinx, Inc.

    Inventor： Khang K. Dao ,  Kyle Corbett

    IPC: G06F17/50

    CPC classification number: G06F17/5022

    Abstract: Approaches for testing a module of a circuit design include tagging flip-flops in a netlist of the module with respective path names of the flip-flops from a hardware description language specification of the module. In simulating with the netlist, event data are captured to a first file. A process determines whether or not event data in the first file matches event data in a second file of event data. In response to a difference determined between the first file and the second file, an earliest occurrence of an event in the first file having an associated signal value of a first signal that does not match an associated signal value of a corresponding event in the second file is determined. The one of the plurality of flip-flops that output the first signal is determined, and the respective path name of the one flip-flop is output.

    Abstract translation: 用于测试电路设计的模块的方法包括：根据模块的硬件描述语言规范，将模块的网表中的触发器标记为具有触发器的相应路径名称的网表。 在与网表模拟时，将事件数据捕获到第一个文件。 进程确定第一文件中的事件数据是否匹配事件数据的第二文件中的事件数据。 响应于在第一文件和第二文件之间确定的差异，第一文件中最早出现的事件具有与第二文件中的相应事件的相关信号值不匹配的第一信号的相关信号值 决心，决意，决定。 确定输出第一信号的多个触发器中的一个，并输出一个触发器的相应路径名。

    Automated pipeline insertion on a bus
    5.
    发明授权
    Automated pipeline insertion on a bus 有权

    公开(公告)号：US10970446B1

    公开(公告)日：2021-04-06

    申请号：US15988448

    申请日：2018-05-24

    Applicant: Xilinx, Inc.

    Inventor： Jeffrey H. Seltzer ,  Khang K. Dao ,  Sabyasachi Das

    IPC: G06F30/3312 ,  G06F30/34 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  G06F119/12

    Abstract: The disclosed approaches process a circuit design having first attributes associated with two or more signals or with sources of the two or more signals. The first attributes specify identifier values. The elements of the circuit design are placed on a target integrated circuit (IC), and timing analysis of the circuit design is performed after placing the elements of the circuit design. In response to the first attributes of the two or more signals or sources specifying equivalent identifier values and a path of at least one of the two or more signals or sources being timing-critical, equal numbers of one or more pipeline registers are inserted on paths of the two or more signals or sources.

    Interface firewall for an integrated circuit of an expansion card
    6.
    发明授权
    Interface firewall for an integrated circuit of an expansion card 有权

    公开(公告)号：US10819680B1

    公开(公告)日：2020-10-27

    申请号：US15915981

    申请日：2018-03-08

    Applicant: Xilinx, Inc.

    Inventor： Sonal Santan ,  Umang Parekh ,  Jeffrey H. Seltzer ,  Khang K. Dao ,  Kyle Corbett

    IPC: H04L29/06 ,  G06F13/42

    Abstract: System and method generally relate to protection of a bussed network. In such a system, an access controller is configured for bussed communication via a communication bus to obtain a current transaction. An interface firewall is coupled for bussed communication with the access controller and configured to check for a fault associated with a transfer. A data processing device is coupled for communication with the interface firewall and configured to execute the current transaction to provide the transfer for the interface firewall. The interface firewall is configured to detect the fault associated with the transfer, to block access to the data processing device associated with the fault, and to communicate a blocked status for the data processing device.

    Software-defined buffer/transposer for general matrix multiplication in a programmable IC
    7.
    发明授权
    Software-defined buffer/transposer for general matrix multiplication in a programmable IC 有权

    公开(公告)号：US11036827B1

    公开(公告)日：2021-06-15

    申请号：US15786346

    申请日：2017-10-17

    Applicant: Xilinx, Inc.

    Inventor： Jindrich Zejda ,  Elliott Delaye ,  Yongjun Wu ,  Aaron Ng ,  Ashish Sirasao ,  Khang K. Dao

    IPC: G06F17/16 ,  G06F7/78 ,  G06F9/30

    Abstract: Methods and apparatus are described for simultaneously buffering and reformatting (e.g., transposing) a matrix for high-speed data streaming in general matrix multiplication (GEMM), which may be implemented by a programmable integrated circuit (IC). Examples of the present disclosure increase the effective double data rate (DDR) memory throughput for streaming data into GEMM digital signal processing (DSP) engine multifold, as well as eliminate slow data reformatting on a host central processing unit (CPU). This may be accomplished through software-defined (e.g., C++) data structures and access patterns that result in hardware logic that simultaneously buffers and reorganizes the data to achieve linear DDR addressing.

    Inclusion and configuration of a transaction converter circuit block within an integrated circuit
    10.
    发明授权
    Inclusion and configuration of a transaction converter circuit block within an integrated circuit 有权

    公开(公告)号：US10346572B1

    公开(公告)日：2019-07-09

    申请号：US15424684

    申请日：2017-02-03

    Applicant: Xilinx, Inc.

    Inventor： Kyle Corbett ,  Khang K. Dao

    IPC: G06F17/50

    Abstract: A method of circuit design can include detecting, using a processor, a transactional inefficiency within trace data including transactions involving a first circuit block of a circuit design and, in response to the detecting, generating a modified version of the circuit design by including a transaction converter circuit block within the circuit design. The transaction converter circuit block can be coupled to the first circuit block and can be adapted to correct the transactional inefficiency.

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