公开(公告)号：US10671785B1

公开(公告)日：2020-06-02

申请号：US15370339

申请日：2016-12-06

Applicant: Xilinx, Inc.

Inventor： Valeria Mihalache ,  Kumar Deepak ,  Saikat Bandyopadhyay ,  Sandeep S. Deshpande ,  Feng Cai

IPC: G06F30/367

Abstract: Simulating a hardware description language design including a core and a testbench can include performing, using a processor, a first compilation of the hardware description language design by generating a compiled core unit for the core, a compiled testbench for the testbench, and synchronization data describing signals crossing a compile checkpoint boundary. A subsequent compilation of the hardware description language design can be performed by reusing the compiled core unit from the first compilation and generating a new compiled testbench for the testbench using the synchronization data.

公开(公告)号：US10235272B2

公开(公告)日：2019-03-19

申请号：US15451068

申请日：2017-03-06

Applicant: Xilinx, Inc.

Inventor： Jason Villarreal ,  Mahesh Sankroj ,  Nikhil A. Dhume ,  Kumar Deepak

IPC: G06F11/36 ,  G06F17/50 ,  G06F11/277 ,  G06F9/44

Abstract: An approach for debugging a circuit implementation of a software specification includes translating a high-level language debugging command into a hardware debugging command that specifies the value(s) of a condition in the circuit implementation, and a storage element(s) at which the value(s) of the condition is stored. The hardware debugging command is transmitted to a debug controller circuit that generates a single clock pulse to the circuit implementation. The debug controller circuit reads a value(s) from the storage element(s) specified by the hardware debugging command and determines whether or not the value(s) satisfies the condition. The debug controller circuit generates another single clock pulse in response to the value(s) read from the storage element(s) not satisfying the condition. Generation of pulses of the clock signal is suspended and data indicative of a breakpoint is output in response to the value(s) read from the storage element(s) satisfying the condition.

公开(公告)号：US20180253368A1

公开(公告)日：2018-09-06

申请号：US15451068

申请日：2017-03-06

Applicant: Xilinx, Inc.

Inventor： Jason Villarreal ,  Mahesh Sankroj ,  Nikhil A. Dhume ,  Kumar Deepak

IPC: G06F11/36 ,  G06F11/277

CPC classification number: G06F11/3636 ,  G06F11/277 ,  G06F11/3628 ,  G06F11/3648 ,  G06F11/3656 ,  G06F11/3664 ,  G06F17/5027

Abstract: An approach for debugging a circuit implementation of a software specification includes translating a high-level language debugging command into a hardware debugging command that specifies the value(s) of a condition in the circuit implementation, and a storage element(s) at which the value(s) of the condition is stored. The hardware debugging command is transmitted to a debug controller circuit that generates a single clock pulse to the circuit implementation. The debug controller circuit reads a value(s) from the storage element(s) specified by the hardware debugging command and determines whether or not the value(s) satisfies the condition. The debug controller circuit generates another single clock pulse in response to the value(s) read from the storage element(s) not satisfying the condition. Generation of pulses of the clock signal is suspended and data indicative of a breakpoint is output in response to the value(s) read from the storage element(s) satisfying the condition.

公开(公告)号：US10754759B1

公开(公告)日：2020-08-25

申请号：US15889001

申请日：2018-02-05

Applicant: Xilinx, Inc.

Inventor： Amitava Majumdar ,  Georgios Tzimpragos ,  Jason Villarreal ,  Kumar Deepak ,  Jayashree Rangarajan

IPC: G06F11/00 ,  G06F11/36

Abstract: An execution circuit inputs a plurality of data units, performs unit operations on the data units, and registers results of the unit operations in response to oscillations of a clock signal. A control circuit controls activation of the unit operations, and outputs a start signal to the execution circuit to activate each unit operation and/or a completion signal to indicate completion of each unit operation. A debug circuit stores breakpoint flags associated with the unit operations. Each breakpoint flag has a state that specifies whether to stop oscillations of the clock signal. The debug circuit further receives the start and/or completion signal and evaluates, while the clock signal oscillates to the execution circuit, a state of the start and/or completion signal and a state of the breakpoint flag associated with the unit operation. Oscillations of the clock signal are stopped in response to the evaluation of the signals.

公开(公告)号：US20180113787A1

公开(公告)日：2018-04-26

申请号：US15334182

申请日：2016-10-25

Applicant: Xilinx, Inc.

Inventor： Jason Villarreal ,  Kumar Deepak

IPC: G06F11/36

CPC classification number: G06F11/3636 ,  G06F11/3632 ,  G06F11/3648

Abstract: Approaches for debugging include receiving by a hardware debug server, a high-level language (HLL) debugging command for setting a breakpoint in an HLL software specification. The hardware debug server translates the HLL debugging command into a hardware debugging command that specifies a condition of a hardware finite state machine that is representation of the software specification. The hardware debugging command is input to a simulator. The simulator adds a conditional breakpoint on the finite state machine in response to the hardware debugging command and executes a simulation of the finite state machine representation. Execution of the simulation is suspended in response to the detecting the condition in the finite state machine.