公开(公告)号：US20240005074A1

公开(公告)日：2024-01-04

申请号：US17810547

申请日：2022-07-01

Applicant: Xilinx, Inc.

Inventor： Pongstorn Maidee

IPC: G06F30/333 ,  G06F30/343 ,  G01R31/28

CPC classification number: G06F30/333 ,  G06F30/343 ,  G01R31/2889

Abstract: An integrated circuit includes a plurality of layers. A subset of the plurality of layers is reserved for implementing user circuitry. At least a portion of a selected layer of the plurality of layers is reserved for debugging.

公开(公告)号：US10909292B1

公开(公告)日：2021-02-02

申请号：US16276336

申请日：2019-02-14

Applicant: Xilinx, Inc.

Inventor： Pongstorn Maidee

IPC: G06F30/34 ,  H03K19/17728 ,  H03K19/173 ,  G06F30/394

Abstract: In an example, a configurable block for a programmable device of a plurality of programmable devices in an integrated circuit (IC) includes a first flip-flop having a data port coupled to an output of an interface block of the programmable device, a clock port coupled to a first clock input, and an output port coupled to a first output. The configurable block further includes a second flip-flop having a data port coupled to the output of the interface block, a clock port coupled to the first clock input, and an output port coupled to a second output, and a first multiplexer having a first input port coupled to the output port of the first flip-flop, and a second input port coupled to the output port of the second flip-flop. The configurable block further includes a third flip-flop having an input port coupled to an output of the first multiplexer, a clock port coupled to a second clock input, and an output port coupled to a third output.

公开(公告)号：US10515047B1

公开(公告)日：2019-12-24

申请号：US15982891

申请日：2018-05-17

Applicant: Xilinx, Inc.

Inventor： Pongstorn Maidee

IPC: G06F13/00 ,  G06F13/14 ,  G06F13/20 ,  G06F13/36 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42

Abstract: Apparatus and method relate to a data channel. In this apparatus, an input circuit is configured to gate a valid input with a ready output to provide a forward token (“f-token”) to a first f-token register of a f-token pipeline and to a counter, and to receive data to a first data register of a data pipeline. An output circuit is configured to gate a ready input with a valid output to provide a return token (“r-token”) to a first r-token register of a r-token pipeline and to a FWFT FIFO, to receive the f-token from a second f-token register of the f-token pipeline to the FWFT FIFO, and to receive the data from a second data register of the data pipeline to the FWFT FIFO. The input circuit receives the r-token from the first r-token register to a second r-token register of the r-token pipeline for the counter.

公开(公告)号：US10002100B2

公开(公告)日：2018-06-19

申请号：US15013696

申请日：2016-02-02

Applicant: Xilinx, Inc.

Inventor： Alireza S. Kaviani ,  Pongstorn Maidee ,  Ivo Bolsens

IPC: G06F13/36 ,  G06F13/362 ,  G06F13/00 ,  G06F13/40

CPC classification number: G06F13/4068 ,  G06F13/362 ,  G06F13/4031

Abstract: An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits in the companion IC coupled between the application circuitry and the second SiP IO circuit.

公开(公告)号：US20170220509A1

公开(公告)日：2017-08-03

申请号：US15013696

申请日：2016-02-02

Applicant: Xilinx, Inc.

Inventor： Alireza S. Kaviani ,  Pongstorn Maidee ,  Ivo Bolsens

IPC: G06F13/40 ,  G06F13/362

CPC classification number: G06F13/4068 ,  G06F13/362 ,  G06F13/4031

Abstract: An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits in the companion IC coupled between the application circuitry and the second SiP IO circuit.