公开(公告)号：US20230169226A1

公开(公告)日：2023-06-01

申请号：US17538497

申请日：2021-11-30

Applicant: Xilinx, Inc.

Inventor： Saikat Bandyopadhyay ,  Shiyao Ge

IPC: G06F30/20 ,  G06F30/333 ,  G01R31/3183

CPC classification number: G06F30/20 ,  G06F30/333 ,  G01R31/318357

Abstract: Approaches for simulating a circuit include receiving simulation input data from a testbench executing on a computer system by a simulator interface executing on the computer system. The simulator interface receives simulation output data the according to a hardware bus protocol specified by a simulated circuit for communication and simulates handshaking with the simulated circuit according to the hardware bus protocol in response to receiving the simulation input data and simulation output data. The simulator interface provides the simulation input data to the simulated circuit by according to the hardware bus protocol and provides the simulation output data to the testbench.

公开(公告)号：US11475199B1

公开(公告)日：2022-10-18

申请号：US17486547

申请日：2021-09-27

Applicant: Xilinx, Inc.

Inventor： Saikat Bandyopadhyay ,  Feng Cai ,  Tapodyuti Mandal ,  Vinayak Thonda ,  Sree Rohith Pulipaka

IPC: G06F30/30 ,  G06F30/392 ,  G06F30/3308 ,  G06F117/08

Abstract: Simulating a circuit design using a data processing system includes partitioning the circuit design into a top-level design and a sub-design along a boundary defined by one or more stream channels coupling a component of the top-level design with the sub-design. The sub-design is extracted from the circuit design and replaced with a stub having a client socket. A wrapper having a server socket is added to the sub-design. The top-level design and the sub-design are compiled into respective simulation kernels. The circuit design is simulated by executing the respective simulation kernels concurrently. The respective kernels communicate over a socket connection established by the client socket and the server socket. In other aspects, the partitioning results in partitions such that one partition is simulated as software and another partition is implemented in circuitry such that the circuit design may be hardware co-simulated.

公开(公告)号：US10437949B1

公开(公告)日：2019-10-08

申请号：US15676104

申请日：2017-08-14

Applicant: Xilinx, Inc.

Inventor： Valeria Mihalache ,  Kumar Deepak ,  Saikat Bandyopadhyay

IPC: G06F9/455 ,  G06F17/50

Abstract: Simulating a circuit design can include detecting, using a processor, an assignment for a signal of a circuit design during a delta cycle of a simulation of the circuit design and comparing, using the processor, a range of the assignment for the signal with a range of an existing event for the signal for the delta cycle. In response to determining that the range of the assignment for the signal and the range of the existing event meet a condition, the existing event is updated, using the processor, resulting in a merged event. The merged event is scheduled for execution for the delta cycle using the processor.

公开(公告)号：US10296673B1

公开(公告)日：2019-05-21

申请号：US14723188

申请日：2015-05-27

Applicant: Xilinx, Inc.

Inventor： Ishita Ghosh ,  Hem C. Neema ,  Jason Villarreal ,  Saikat Bandyopadhyay ,  Kumar Deepak

IPC: G06F17/50

Abstract: For generating code for simulation of a circuit design, a hardware description language (HDL) description and a high-level language (HLL) description of portions of the circuit design are input. The HLL description specifies a first function and the HDL description includes a call to the first function. A wrapper is generated for the first function. The wrapper has an associated stack frame and includes code that stores in the stack frame values of arguments specified by the call to the first function and code that calls the first function. An HLL simulation specification is generated from the HDL description. The HLL simulation specification includes a call to the first HLL wrapper in place of the call to the first function. The HLL simulation specification, the first HLL wrapper, and the HLL description are compiled into executable program code.

公开(公告)号：US09582619B1

公开(公告)日：2017-02-28

申请号：US14058505

申请日：2013-10-21

Applicant: Xilinx, Inc.

Inventor： David K. Liddell ,  Feng Cai ,  Saikat Bandyopadhyay

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F17/5045

Abstract: An approach for simulating a block of a circuit design includes using a row-matching table and a port state vector. The row-matching table includes a plurality of rows, and each row includes encoded input match patterns corresponding to a plurality of input ports of the block and an associated output value. The port state vector includes input state codes associated with the input ports. In response to an update of an input signal value at one of the input ports during simulation, the input state code associated with the one input port is updated according to the updated input signal value. A bit-to-bit pattern match is performed for each bit in the port state vector to a corresponding bit in the encoded input match patterns in one or more rows of the row-matching table. The associated output value of a matching row is selected as a new output value.

Abstract translation: 用于模拟电路设计的块的方法包括使用行匹配表和端口状态向量。 行匹配表包括多行，并且每行包括与块的多个输入端口对应的编码输入匹配模式和相关联的输出值。 端口状态向量包括与输入端口相关联的输入状态代码。 响应于在模拟期间在输入端口之一处的输入信号值的更新，与一个输入端口相关联的输入状态代码根据更新的输入信号值被更新。 对端口状态向量中的每个位执行位对位模式匹配，使其与行匹配表的一行或多行中的编码输入匹配模式中的相应位相对应。 匹配行的关联输出值被选为新的输出值。

公开(公告)号：US09223910B1

公开(公告)日：2015-12-29

申请号：US14159855

申请日：2014-01-21

Applicant: Xilinx, Inc.

Inventor： Ishita Ghosh ,  Saikat Bandyopadhyay ,  Kumar Deepak ,  Hem C. Neema ,  David K. Liddell

IPC: G06F17/50

CPC classification number: G06F17/5022

Abstract: A method for compiling an HDL specification for simulation of a circuit design is disclosed. The circuit design is elaborated from the HDL specification and memory locations are allocated for formals and actuals of the elaborated circuit design. For each port having a formal and an actual that are compatible, the allocating of memory locations sets a reference pointer for the formal and a reference pointer for the actual to reference a same one of the memory locations. For each port having a formal and an actual that are incompatible, the allocating of memory locations sets the reference pointer for the formal and the reference pointer for the actual to reference different respective ones of the memory locations. Simulation code modeling the elaborated circuit design is generated that updates a formal and actual of a port that are compatible using a single write operation to the referenced memory location.

Abstract translation: 公开了一种用于编译用于模拟电路设计的HDL规范的方法。 电路设计由HDL规范进行阐述，内存位置分配给精密电路设计的正式和实际。 对于具有兼容的形式和实际的每个端口，存储器位置的分配设置用于形式的参考指针和用于实际引用相同存储器位置的引用指针。 对于具有不兼容的形式和实际的每个端口，存储器位置的分配设置形式的参考指针和用于实际引用的参考指针以引用不同的相应存储器位置。 生成针对详细电路设计的仿真代码建模，其将使用单个写入操作兼容的端口的正式和实际更新到引用的存储器位置。