公开(公告)号：US11355412B2

公开(公告)日：2022-06-07

申请号：US16147286

申请日：2018-09-28

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Gamal Refai-Ahmed ,  Henley Liu ,  Myongseob Kim ,  Tien-Yu Lee ,  Suresh Ramalingam ,  Cheang-Whang Chang

IPC: H01L23/367 ,  H01L23/427 ,  H01L25/18 ,  H01L25/00 ,  H01L21/48 ,  H01L25/065 ,  H01L25/07

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.

公开(公告)号：US11315858B1

公开(公告)日：2022-04-26

申请号：US16903376

申请日：2020-06-17

Applicant: XILINX, INC.

Inventor： Yu Hsiang Sun ,  Suresh Ramalingam ,  Tien-Yu Lee ,  Jaspreet Singh Gandhi

IPC: H01L23/498 ,  H01L23/00

Abstract: A chip package assembly having robust solder connections are described herein. In one example, a chip package assembly is provided that includes an integrated circuit (IC) die and a package substrate. Solder pads are arranged to connect to pillars of the IC die via solder connections. Solder resist in the corners of the package substrate and surrounding the solder connections may be inhibited from cracking isolating the portion of the solder resist surrounding the solder pads and/or by providing an offset between centerlines of the pillars and solder pads.

公开(公告)号：US10930611B1

公开(公告)日：2021-02-23

申请号：US16523950

申请日：2019-07-26

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Tien-Yu Lee

IPC: H01L23/00

Abstract: An integrated circuit assembly having an improved solder connection, and methods for fabricating the same are provided that utilize platelets within the solder connections to inhibit solder connection failure, thus providing a more robust solder interface. In one example, an integrated circuit assembly is provided that includes a package substrate having a first plurality of contact pads exposed on a first surface of the package substrate and a second plurality of contact pads exposed on a second surface of the package substrate. The second plurality of contact pads have a pitch that is greater than a pitch of the first plurality of contact pads. Interconnect circuitry is disposed in the package substrate and couples the first and second pluralities of contact pads. At least a first contact pad of the second plurality of contact pads includes a solder ball disposed directly in contact with a palladium layer.