公开(公告)号：US20130117538A1

公开(公告)日：2013-05-09

申请号：US13730839

申请日：2012-12-29

Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

公开(公告)号：US20120198210A1

公开(公告)日：2012-08-02

申请号：US13444090

申请日：2012-04-11

Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: A processor. The processor includes a first register for storing a first packed data, a decoder, and a functional unit. The decoder has a control signal input. The control signal input is for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation. The second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder and the register. The functional unit is for performing the pack operation and the unpack operation using the first packed data. The processor also supports a move operation.

Abstract translation: 处理器 处理器包括用于存储第一打包数据的第一寄存器，解码器和功能单元。 解码器具有控制信号输入。 控制信号输入用于接收第一控制信号和第二控制信号。 第一控制信号用于指示包装操作。 第二控制信号用于指示解封装操作。 功能单元耦合到解码器和寄存器。 功能单元用于使用第一打包数据执行包操作和拆包操作。 处理器还支持移动操作。

公开(公告)号：US07966482B2

公开(公告)日：2011-06-21

申请号：US11451906

申请日：2006-06-12

Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC: G06F9/315

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element.

Abstract translation: 一种装置包括指令解码器，第一和第二源寄存器和耦合到解码器的电路，用于从源寄存器接收压缩数据，并响应于解码器接收到的包指令对压缩数据进行打包。 从第一源寄存器接收第一打包数据元素和第二打包数据元素。 从第二源寄存器接收第三压缩数据元素和第四打包数据元素。 所述电路包装将每个打包数据元素的一部分包装到目的地寄存器中，其结果是来自与来自第一打包数据元素的部分相邻的第二打包数据元素的部分，以及来自与该部分相邻的第四打包数据元素的部分 从第三个打包的数据元素。

公开(公告)号：US5666298A

公开(公告)日：1997-09-09

申请号：US701564

申请日：1996-08-22

Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC: G06F7/00 ,  G06F5/01 ,  G06F7/76 ,  G06F9/30 ,  G06F9/315 ,  G06F9/38

CPC classification number: G06F7/76 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30167

Abstract: A processor. The processor includes a decoder being coupled to receive a control signal. The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data shift operation is to be performed. The processor further includes a circuit being coupled to the decoder. The circuit is for shifting a first packed data being stored at the first location by a value being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.

Abstract translation: 处理器 处理器包括被耦合以接收控制信号的解码器。 控制信号具有第一源地址，第二源地址，目的地地址和操作字段。 第一个源地址对应于第一个位置。 第二源地址对应于第二位置。 目的地址对应于第三个位置。 操作字段指示将执行一种打包数据移位操作。 处理器还包括耦合到解码器的电路。 电路用于将存储在第一位置的第一打包数据移位存储在第二位置的值。 电路还用于将相应的结果打包数据传送到第三位置。

公开(公告)号：US08639914B2

公开(公告)日：2014-01-28

申请号：US13730831

申请日：2012-12-29

Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC: G06F15/80

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

Abstract translation: 一种装置包括指令解码器，第一和第二源寄存器以及耦合到解码器的电路，用于从源寄存器接收压缩数据，并根据解码器接收到的解包指令对打包数据进行解包。 从第一源寄存器接收第一打包数据元素和第三打包数据元素。 从第二源寄存器接收第二打包数据元素和第四打包数据元素。 所述电路将打包的数据元素复制到目的地寄存器中，其中与第一打包数据元素相邻的第二打包数据元素，与第二打包数据元素相邻的第三打包数据元素以及与第三打包数据元素相邻的第四打包数据元素 数据元素。

公开(公告)号：US20130124833A1

公开(公告)日：2013-05-16

申请号：US13730846

申请日：2012-12-29

Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

公开(公告)号：US20130117540A1

公开(公告)日：2013-05-09

申请号：US13730832

申请日：2012-12-29

Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

Abstract translation: 一种装置包括指令解码器，第一和第二源寄存器以及耦合到解码器的电路，用于从源寄存器接收压缩数据，并根据解码器接收到的解包指令对打包数据进行解包。 从第一源寄存器接收第一打包数据元素和第三打包数据元素。 从第二源寄存器接收第二打包数据元素和第四打包数据元素。 所述电路将打包的数据元素复制到目的地寄存器中，其中与第一打包数据元素相邻的第二打包数据元素，与第二打包数据元素相邻的第三打包数据元素以及与第三打包数据元素相邻的第四打包数据元素 数据元素。

公开(公告)号：US20110283152A1

公开(公告)日：2011-11-17

申请号：US12780904

申请日：2010-05-16

Applicant: Daniel Citron ,  Moshe Klausner ,  Aharon Kupershtok ,  Yousef Shajrawi ,  Yaakov Yaari

Inventor： Daniel Citron ,  Moshe Klausner ,  Aharon Kupershtok ,  Yousef Shajrawi ,  Yaakov Yaari

IPC: G06F11/34

CPC classification number: G06F11/3466 ,  G06F11/3404 ,  G06F11/3447 ,  G06F12/0815 ,  G06F2201/865

Abstract: Systems and methods for cache optimization are provided. The method comprises tracing objects instantiated during execution of a program code under test according to type of access by one or more threads running in parallel, wherein said tracing provides information about order in which different instances of one or more objects are accessed by said one or more threads and whether the type of access is a read operation or a write operation; and utilizing tracing information to build a temporal relationship graph (TRG) for the accessed objects, wherein the objects are represented by nodes in the TRG and at least two types of edges for connecting the nodes are defined.

Abstract translation: 提供了缓存优化的系统和方法。 该方法包括根据由并行运行的一个或多个线程的访问类型来跟踪在执行被测程序代码期间实例化的对象，其中所述跟踪提供关于一个或多个对象的不同实例被所述一个或多个对象访问的顺序的信息， 更多线程以及访问类型是读操作还是写操作; 并且利用跟踪信息为所访问的对象建立时间关系图（TRG），其中所述对象由所述TRG中的节点表示，并且用于连接所述节点的至少两种类型的边缘被定义。

公开(公告)号：US07480686B2

公开(公告)日：2009-01-20

申请号：US10846726

申请日：2004-05-14

Applicant: Derrick Chu Lin ,  Punit Minocha ,  Alexander D. Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Srinivas Chennupaty

Inventor： Derrick Chu Lin ,  Punit Minocha ,  Alexander D. Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Srinivas Chennupaty

IPC: G06F5/01

CPC classification number: G06F7/762 ,  G06F7/76 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30167

Abstract: A method and apparatus for performing a shift operation on packed data elements having multiple values. One embodiment includes accessing the shift control signal of a first format from a memory. The shift control signal identifyies a first packed shift operation and whether the shift positions are byte positions or bit positions, and causes a processor to execute a set of control signals of a second format, thereby accessing the packed data, shifting the packed data by the number of shift positions according to the first packed shift operation, generating a first replacement data for one of the number of positions, and producing a shifted first packed data comprising the first replacement data.

Abstract translation: 一种用于对具有多个值的压缩数据元素执行移位操作的方法和装置。 一个实施例包括从存储器访问第一格式的移位控制信号。 移位控制信号识别第一打包移位操作以及移位位置是字节位置还是位位置，并使处理器执行一组第二格式的控制信号，从而访问打包数据，将打包数据移位 根据第一打包移位操作的移位位置的数量，产生用于多个位置之一的第一替换数据，并且产生包括第一替换数据的移位的第一打包数据。

公开(公告)号：US07451169B2

公开(公告)日：2008-11-11

申请号：US11454749

申请日：2006-06-15

Applicant: Derrick Chu Lin ,  Punit Minocha ,  Alexander D. Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

Inventor： Derrick Chu Lin ,  Punit Minocha ,  Alexander D. Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC: G06F5/01

CPC classification number: G06F7/762 ,  G06F5/01 ,  G06F7/49994 ,  G06F7/76 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3885

Abstract: A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.

Abstract translation: 一种用于在处理器中提供对具有多个值的压缩数据元素进行移位操作的方法和装置。 所述装置具有多个多路复用器，所述多个多路复用器中的每一个具有第一输入，第二输入，选择输入和输出。 表示在第一总线上的移位的打包中间结果的多个比特中的每一个被耦合到对应的第一输入。 表示多个值之一的替换位的多个比特中的每一个被耦合到对应的第二输入。 由校正电路驱动的多个比特中的每一个被耦合到对应的选择输入。 每个输出对应于移位包装结果的一位。