公开(公告)号：US08609477B2

公开(公告)日：2013-12-17

申请号：US13499353

申请日：2011-04-26

申请人： Youngsuk Song ,  Seungjin Choi ,  Seongyeol Yoo

发明人： Youngsuk Song ,  Seungjin Choi ,  Seongyeol Yoo

IPC分类号： H01L21/84

CPC分类号： H01L27/1288 ,  G02F2001/134372 ,  H01L27/1214

摘要： A manufacturing method for an array substrate with a fringe field switching (FFS) type thin film transistor (TFT) liquid crystal display (LCD) includes the following steps. A pattern of a gate line (1), a gate electrode, a common electrode (6) and a common electrode line (5) is formed by patterning a first transparent conductive film and a first metal film formed successively on a transparent substrate. Contact holes of the gate line in the pad area and a semiconductor pattern are formed through a patterning process after a gate insulator film, and a semiconductor film and a doped semiconductor film are formed successively. A second metal film is deposited and patterned. A second transparent conductive film is deposited and a lift-off process is performed. And then, a pattern of a source electrode, a drain electrode, a TFT channel and a pixel electrode (4) is formed by etching the exposed second metal film and the doped semiconductor film.

摘要翻译： 具有条纹场切换（FFS）型薄膜晶体管（TFT）液晶显示器（LCD）的阵列基板的制造方法包括以下步骤。 通过对在透明基板上连续形成的第一透明导电膜和第一金属膜进行图案化，形成栅极线（1），栅电极，公共电极（6）和公共电极线（5）的图案。 在栅绝缘膜之后通过图案化工艺形成焊盘区域中的栅极线的接触孔和半导体图案，并且依次形成半导体膜和掺杂半导体膜。 沉积和图案化第二金属膜。 沉积第二透明导电膜并执行剥离过程。 然后，通过蚀刻暴露的第二金属膜和掺杂半导体膜来形成源电极，漏电极，TFT沟道和像素电极（4）的图案。

公开(公告)号：US08586453B2

公开(公告)日：2013-11-19

申请号：US13248908

申请日：2011-09-29

申请人： Seongyeol Yoo ,  Youngsuk Song ,  Seungjin Choi ,  Zhanfeng Cao

发明人： Seongyeol Yoo ,  Youngsuk Song ,  Seungjin Choi ,  Zhanfeng Cao

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： G03F7/0035 ,  H01L27/124 ,  H01L27/1288

摘要： A method for fabricating a thin film pattern and a method for fabricating an array substrate are provided. The method for fabricating a thin film pattern comprises: forming a first film and a second film sequentially; applying a layer of photoresist on the second film; forming a photoresist pattern comprising a totally left region, a partially left region and a totally removed region; performing a first wet etching on the second film in the totally removed region; performing a first dry etching on the first film in the totally removed region to form a first pattern, and etching the photoresist layer to remove the photoresist in the partially left region to expose the second film in the partially left region; performing a second wet etching on the second film in the partially left region; performing a second dry etching to form a second pattern; and removing the residual photoresist.

摘要翻译： 提供一种薄膜图案的制造方法和阵列基板的制造方法。 制造薄膜图案的方法包括：依次形成第一膜和第二膜; 在第二膜上施加一层光致抗蚀剂; 形成包括完全左区域，部分左区域和完全去除区域的光致抗蚀剂图案; 在完全去除的区域中对第二膜执行第一湿蚀刻; 在完全去除的区域中对第一膜执行第一干蚀刻以形成第一图案，并蚀刻光致抗蚀剂层以去除部分左侧区域中的光致抗蚀剂，以暴露部分左侧区域中的第二膜; 在部分左侧区域中的第二膜上进行第二湿蚀刻; 执行第二干蚀刻以形成第二图案; 并除去残留的光致抗蚀剂。

公开(公告)号：US08703510B2

公开(公告)日：2014-04-22

申请号：US13278360

申请日：2011-10-21

申请人： Youngsuk Song ,  Seungjin Choi ,  Seongyeol Yoo

发明人： Youngsuk Song ,  Seungjin Choi ,  Seongyeol Yoo

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/331 ,  H01L21/8222

CPC分类号： H01L27/1288 ,  G02F2001/136236

摘要： An embodiment of the invention provides a method for manufacturing an array substrate, wherein the procedure for forming a data line, an active layer with a channel, a source electrode, a drain electrode and a pixel electrode comprises applying a photoresist on a data line metal thin film and performing exposure and development processes by using a multi-tone mask so as to form a photoresist pattern including a third thickness region, a second thickness region and a first thickness region whose thicknesses are successively increased, the third thickness region at least corresponding to the pixel electrode, the second thickness region corresponding to the data line, the active layer, the source electrode and the drain electrode, and the first thickness region corresponding to the other regions.

摘要翻译： 本发明的一个实施例提供了一种用于制造阵列基板的方法，其中用于形成数据线的步骤，具有沟道的有源层，源电极，漏电极和像素电极包括在数据线金属 薄膜，并通过使用多色调掩模进行曝光和显影处理，以形成包括第三厚度区域，第二厚度区域和厚度依次增加的第一厚度区域的光致抗蚀剂图案，第三厚度区域至少相应地 对应于数据线，有源层，源电极和漏电极的第二厚度区域和对应于其它区域的第一厚度区域到像素电极。

公开(公告)号：US08497966B2

公开(公告)日：2013-07-30

申请号：US12836028

申请日：2010-07-14

申请人： Seungjin Choi ,  Youngsuk Song ,  Seongyeol Yoo

发明人： Seungjin Choi ,  Youngsuk Song ,  Seongyeol Yoo

IPC分类号： G02F1/1343

CPC分类号： H01L27/1288 ,  G02F1/134363 ,  G02F2001/134372 ,  H01L27/1214

摘要： A manufacturing method for an FFS type TFT-LCD array substrate comprises: depositing a first metal film on a transparent substrate, and form a gate line, a gate electrode and a common electrode line by a first patterning process; depositing a gate insulating layer, an active layer film and a second metal film sequentially and patterning the second metal film and the active layer film by a second patterning process; Step 3 depositing a first transparent conductive film and patterning the first transparent conductive film, the second metal film and the active layer film by a third patterning process; depositing a passivation layer, forming a connection hole by patterning the passivation layer through the fourth patterning process, performing an ashing process on photoresist used in the fourth patterning process, depositing a second transparent conductive layer on the remaining photoresist, and forming a common electrode by a lifting-off process.

摘要翻译： 一种FFS型TFT-LCD阵列基板的制造方法，其特征在于，在第一图案形成工序中，在透明基板上淀积第一金属膜，形成栅极线，栅电极，公共电极线; 依次沉积栅极绝缘层，有源层膜和第二金属膜，并通过第二图案化工艺图案化第二金属膜和有源层膜; 步骤3沉积第一透明导电膜并通过第三图案化工艺图案化第一透明导电膜，第二金属膜和有源层膜; 沉积钝化层，通过第四图案化工艺图案化钝化层形成连接孔，在第四图案化工艺中使用的光致抗蚀剂上进行灰化处理，在剩余光致抗蚀剂上沉积第二透明导电层，并通过 起吊过程。

公开(公告)号：US08298878B2

公开(公告)日：2012-10-30

申请号：US12784759

申请日：2010-05-21

申请人： Seongyeol Yoo ,  Seungjin Choi ,  Youngsuk Song

发明人： Seongyeol Yoo ,  Seungjin Choi ,  Youngsuk Song

IPC分类号： H01L21/00

CPC分类号： H01L27/1288 ,  H01L27/1214

摘要： The embodiment of the invention provides a manufacturing method for a thin film transistor liquid crystal display (TFT-LCD) array substrate, the manufacturing method comprises: step 1, depositing a transparent conductive film, a source/drain metal film and a doped semiconductor film on a transparent substrate sequentially, forming patterns of a doped semiconductor layer, a source electrode and a drain electrode of a thin film transistor, a data line and a pixel electrode by a first patterning process, wherein the doped semiconductor layer remains on the source electrode and the drain electrode; Step 2, depositing a semiconductor film on the whole transparent substrate after Step 1, forming a pattern of a semiconductor layer which includes a channel of the thin film transistor by a second patterning process; Step 3, depositing an insulating film and a gate metal film on the whole transparent substrate after Step 2, forming patterns of a gate line and a gate electrode of the thin film transistor by a third patterning process, wherein the gate electrode is located above the channel of the thin film transistor.

摘要翻译： 本发明的实施例提供一种薄膜晶体管液晶显示（TFT-LCD）阵列基板的制造方法，其制造方法包括：步骤1，沉积透明导电膜，源/漏金属膜和掺杂半导体膜 在透明基板上顺序地通过第一图案化工艺形成薄膜晶体管，数据线和像素电极的掺杂半导体层，源电极和漏电极的图案，其中掺杂半导体层保留在源极上 和漏电极; 步骤2，在步骤1之后，在整个透明衬底上沉积半导体膜，通过第二图案化工艺形成包括薄膜晶体管的沟道的半导体层的图案; 步骤3，在步骤2之后，在整个透明基板上沉积绝缘膜和栅极金属膜，通过第三图案化工艺形成薄膜晶体管的栅极线和栅电极的图案，其中栅电极位于 通道的薄膜晶体管。

公开(公告)号：US20100075450A1

公开(公告)日：2010-03-25

申请号：US12565953

申请日：2009-09-24

申请人： Seungjin Choi ,  Youngsuk Song ,  Seongyeol Yoo

发明人： Seungjin Choi ,  Youngsuk Song ,  Seongyeol Yoo

IPC分类号： H01L21/28

CPC分类号： H01L27/1288 ,  G02F1/1368 ,  H01L27/1214

摘要： A method for manufacturing an array substrate of liquid crystal display comprising the following steps: providing a substrate having gate lines, a gate insulating layer and an active layer pattern formed thereon in this order; depositing a first transparent conductive layer and a source/drain metal layer in this order on the substrate; forming a photoresist pattern layer on the source/drain metal layer through a triple-tone mask; performing a wet-etching process on the source/drain metal layer and the first transparent conductive layer exposed from the photoresist pattern layer; performing a first ashing process on the photoresist pattern layer and performing a dry-etching process on the source/drain metal layer, the first transparent conductive layer and the active layer pattern exposed by the first ashing process; performing a second ashing process on the photoresist pattern layer and performing a wet-etching process on the source/drain metal layer exposed by the second ashing process; and removing the remaining photoresist pattern layer. According to the invention, the over-etching on the TFT channel region can be reduced and the display quality of the liquid crystal display can be ensured.

摘要翻译： 一种制造液晶显示器阵列基板的方法，包括以下步骤：依次提供具有栅极线，栅极绝缘层和有源层图案的基板; 在衬底上依次沉积第一透明导电层和源极/漏极金属层; 通过三色调掩模在源极/漏极金属层上形成光致抗蚀剂图案层; 对源极/漏极金属层和从光致抗蚀剂图案层露出的第一透明导电层进行湿法蚀刻工艺; 在所述光致抗蚀剂图案层上进行第一灰化处理，对所述源极/漏极金属层，所述第一透明导电层和所述有源层图案进行第一灰化处理曝光的干蚀刻处理; 在光致抗蚀剂图案层上进行第二灰化处理，并对通过第二灰化处理暴露的源极/漏极金属层进行湿法蚀刻处理; 并除去剩余的光致抗蚀剂图案层。 根据本发明，可以减少TFT沟道区上的过蚀刻，并且可以确保液晶显示器的显示质量。

公开(公告)号：US07834360B2

公开(公告)日：2010-11-16

申请号：US12126253

申请日：2008-05-23

申请人： Seungjin Choi ,  Youngsuk Song

发明人： Seungjin Choi ,  Youngsuk Song

IPC分类号： H01L27/14

CPC分类号： H01L27/124 ,  G02F1/136259

摘要： The present invention relates to a thin film transistor array substrate comprising a gate line and a data line that are separated by an insulting layer and intersecting each other to define a pixel, wherein a data auxiliary line is disposed adjacent to an intersection portion between the data line and the gate line, and both ends of the data auxiliary line are on two sides of the intersection portion and connected with the data lines, respectively.

摘要翻译： 薄膜晶体管阵列基板技术领域本发明涉及一种薄膜晶体管阵列基板，包括由绝缘层分隔开并彼此相交以限定像素的栅极线和数据线，其中数据辅助线邻近数据之间的相交部分设置 线和栅极线，数据辅助线的两端分别在交叉部分的两侧并与数据线连接。

公开(公告)号：US20090085034A1

公开(公告)日：2009-04-02

申请号：US12126253

申请日：2008-05-23

申请人： Seungjin Choi ,  Youngsuk Song

发明人： Seungjin Choi ,  Youngsuk Song

IPC分类号： H01L27/12

CPC分类号： H01L27/124 ,  G02F1/136259

摘要： The present invention relates to a thin film transistor array substrate comprising a gate line and a data line that are separated by an insulting layer and intersecting each other to define a pixel, wherein a data auxiliary line is disposed adjacent to an intersection portion between the data line and the gate line, and both ends of the data auxiliary line are on two sides of the intersection portion and connected with the data lines, respectively.

摘要翻译： 薄膜晶体管阵列基板技术领域本发明涉及一种薄膜晶体管阵列基板，包括由绝缘层分隔开并彼此相交以限定像素的栅极线和数据线，其中数据辅助线邻近数据之间的相交部分设置 线和栅极线，数据辅助线的两端分别在交叉部分的两侧并与数据线连接。