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17 条记录 (耗时 0.018 秒)

    Encoding rate detection method and encoding rate detection device
    11.
    发明授权
    Encoding rate detection method and encoding rate detection device 失效
    编码率检测方法和编码速率检测装置

    公开(公告)号：US06728926B1

    公开(公告)日：2004-04-27

    申请号：US09831636

    申请日：2001-05-11

    申请人： Takashi Kakemizu ,  Takehiro Kamada ,  Yuji Nakai

    发明人： Takashi Kakemizu ,  Takehiro Kamada ,  Yuji Nakai

    IPC分类号： H03M1300

    CPC分类号： H03M13/33 ,  H03M13/01 ,  H04L1/0046 ,  H04L7/041

    摘要： In accordance with a rate detecting method for detecting a predetermined rate at which a received signal has been coded, the coded signal is decoded based on a first synchronizing signal having a frequency corresponding to a first rate such that a first decoded signal (ST11) is generated and then it is judged whether or not synchronization is determined for the first decoded signal (ST12). If the synchronization cannot be determined, there is generated only a second synchronizing signal having a frequency corresponding to a second rate having a difference between itself and a first rate which is smaller than a permissible value of the rate determined by the lower and upper values of the rate (ST13, ST17).

    摘要翻译： 根据用于检测接收信号已被编码的预定速率的速率检测方法，基于具有与第一速率对应的频率的第一同步信号来解码编码信号，使得第一解码信号（ST11）为 然后判断是否确定了第一解码信号的同步（ST12）。 如果不能确定同步，则只产生第二同步信号，该第二同步信号具有对应于第二速率的频率，该第二速率具有自身与第一速率之间的差值，该第一速率小于由下限和下限值确定的速率的允许值 率（ST13，ST17）。

    Semiconductor integrated circuit device
    15.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US07057968B2

    公开(公告)日：2006-06-06

    申请号：US11075739

    申请日：2005-03-10

    申请人： Naoki Kuroda ,  Yuji Nakai

    发明人： Naoki Kuroda ,  Yuji Nakai

    IPC分类号： G11C8/00

    CPC分类号： G11C11/413 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C11/412 ,  G11C2207/107

    摘要： Logic circuits access a memory block by way of an access circuit. The memory block, which is formed of a mixed configuration of DRAMs and an SRAM, realizes the desired memory space. A data output register is provided at the output side of the SRAM so as to synchronize data output timing from the DRAMs with data output timing from the SRAM.

    摘要翻译： 逻辑电路通过访问电路访问存储块。 由DRAM和SRAM的混合配置形成的存储器块实现期望的存储器空间。 在SRAM的输出侧提供数据输出寄存器，以使来自DRAM的数据输出定时与来自SRAM的数据输出定时同步。

    Semiconductor integrated circuit device having a common DRAM block accessed by a plurality of logic circuits
    16.
    发明授权
    Semiconductor integrated circuit device having a common DRAM block accessed by a plurality of logic circuits 有权
    具有由多个逻辑电路访问的公共DRAM块的半导体集成电路器件

    公开(公告)号：US06990043B2

    公开(公告)日：2006-01-24

    申请号：US11074897

    申请日：2005-03-09

    申请人： Naoki Kuroda ,  Yuji Nakai

    发明人： Naoki Kuroda ,  Yuji Nakai

    IPC分类号： G11C8/18

    CPC分类号： G11C7/10 ,  G11C7/1006 ,  G11C2207/107

    摘要： A plurality of logic circuits access a DRAM block by way of an access circuit. The operation clock for the DRAM block is set at a higher frequency than the system clock for the logic circuits. Outputs of a first bit width from the logic circuits are subjected to serial/parallel conversion into data of a second bit width and the data is written into the DRAM block.

    摘要翻译： 多个逻辑电路通过访问电路访问DRAM块。 DRAM块的操作时钟设置在比逻辑电路的系统时钟更高的频率上。 来自逻辑电路的第一位宽的输出经过串行/并行转换为第二位宽的数据，并将数据写入DRAM块。